3D Ferroelectric Tunnel Junction Memory for In-Memory MAC
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Solution Overview
Problem
Limited memory bandwidth and high power consumption are significant challenges in machine learning systems, particularly in deep neural networks, due to the bottleneck at the interface between processor chips and DRAMs, leading to increased latency and inefficient data movement.
Innovation Solution
Integration of memory and processing in a three-dimensional NOR-based memory device that performs matrix vector multiplication and accumulation operations directly in the memory array, using ferroelectric tunnel junctions to enhance efficiency and reduce the need for data transfer to processing units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is stored in DRAM and processed by separate processor chips, then storage density and processing capability are achieved, but memory bandwidth is limited and power consumption increases
Solution Approach 1:
The patent merges memory and processing functions into a single integrated device. The memory array performs matrix-vector multiplication operations directly on stored data, eliminating the need to transfer data between separate memory and processing units. This combination resolves the bandwidth and power consumption issues by removing the data movement bottleneck between DRAM and processor chips.
Solution Approach 2:
The patent transitions from traditional two-dimensional planar memory architecture to a three-dimensional vertically-stacked architecture. Multiple memory layers are stacked vertically with shared bit lines, enabling higher storage density and allowing processing operations to be performed in three-dimensional space. This dimensional change increases the amount of data that can be processed simultaneously while reducing the physical distance for data access.
2Quantity of substance
If large amounts of memory are added to processor chips, then storage capacity increases, but chip area becomes expensive and integration becomes difficult
Solution Approach 1:
The patent uses three-dimensional vertical stacking to increase memory capacity without proportionally increasing chip area. Multiple memory layers are stacked vertically above a small footprint, achieving high storage density. The vertically-stacked architecture allows terabytes of storage to be integrated in a compact form factor, avoiding the area expenses of adding large amounts of memory to traditional two-dimensional processor chips.
3Speed
If data is constantly transferred between memory and processor, then computation can proceed, but latency increases and bandwidth is bottlenecked
Solution Approach 1:
The patent combines memory storage and processing operations in a single integrated device. The memory array directly performs matrix-vector multiplication on stored data, eliminating the time-consuming data transfer between separate memory and processing units. This merging enables computation to proceed at the speed of the processing operations themselves, removing the latency bottleneck of constant data transfer.
4Use of energy by moving object
If ferroelectric tunnel junctions are used for in-memory computing, then energy efficiency improves, but device complexity increases
Solution Approach 1:
The patent uses ferroelectric tunnel junctions that exploit changes in electrical parameters (resistance states) to perform computing operations. The FTJs utilize ferroelectric polarization switching to modulate tunnel current, enabling multiplication operations through changes in electrical resistance. This parameter-based operation achieves high energy efficiency by performing computations through passive electrical property changes rather than active switching, reducing power consumption despite the complex device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves energy efficiency by 5-10 times and reduces power consumption, enabling efficient matrix vector multiplication and accumulation operations within the memory device.
Implementation Method 1
a ferroelectric thin film is located between two electrodes. The polarization is switched by applying an electric field between the electrodes.
Implementation Method 2
The tunnel transmission is modulated by the ferroelectric polarization.
Data Source
AI summary
Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory cell array has memory cells arranged vertically above a semiconductor substrate. Each memory cell stores a weight using a ferroelectric tunnel junction (FTJ) device as a storage element. Local digit lines connect to terminals of the memory cells. The local digit lines extend vertically above the substrate. Select transistors connect to the local digit lines. Select lines control the select transistors, and are used to encode an input pattern to multiply by the stored weights. Accumulation circuitry sums output currents from the memory cells.