3D Fuse Architectures for Area Reduction and Soft Error Resistance
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Solution Overview
Problem
Two-dimensional fuse architectures face challenges in efficiently integrating fuse arrays and fuse circuitry on a semiconductor substrate, leading to complex designs, increased area usage, and vulnerability to soft errors.
Innovation Solution
The implementation of three-dimensional fuse architectures, where fuse arrays and fuse circuitry are configured with a substrate, allowing for overlapping structures and simpler latches, reducing area usage and minimizing soft error risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional fuse architectures are used, then fuse arrays and fuse circuitry can be integrated on a semiconductor substrate, but the design becomes complex and area usage increases
Solution Approach 1:
The patent transitions from a two-dimensional fuse architecture to a three-dimensional fuse architecture. The fuse array is arranged in multiple stacked layers on the semiconductor substrate, with fuse circuitry positioned between the layers. This vertical stacking enables efficient integration while maintaining simpler circuit designs, as the three-dimensional arrangement naturally reduces the need for complex broadcast and load schemes required in planar designs.
2Ease of manufacture
If two-dimensional fuse architectures are used, then fuse arrays and fuse circuitry can be integrated on a semiconductor substrate, but area usage increases
Solution Approach 1:
The patent transitions from a two-dimensional fuse architecture to a three-dimensional fuse architecture. The fuse array is arranged in multiple stacked layers on the semiconductor substrate, with fuse circuitry positioned between the layers. This vertical stacking enables efficient integration while maintaining simpler circuit designs, as the three-dimensional arrangement naturally reduces the need for complex broadcast and load schemes required in planar designs.
Solution Approach 2:
The patent implements a nested structure where fuse circuitry is positioned between stacked layers of fuse arrays. The first fuse array layer is positioned above the semiconductor substrate, with fuse circuitry disposed between the substrate and the first layer. A second fuse array layer can be positioned above the first layer, creating a nested, space-efficient configuration that maximizes substrate utilization while minimizing overall area usage.
3Ease of manufacture
If two-dimensional fuse architectures are used, then fuse arrays can be integrated on a semiconductor substrate, but vulnerability to soft errors increases
Solution Approach 1:
The patent transitions from a two-dimensional fuse architecture to a three-dimensional fuse architecture. The fuse array is arranged in multiple stacked layers on the semiconductor substrate, with fuse circuitry positioned between the layers. This vertical stacking enables efficient integration while maintaining simpler circuit designs, as the three-dimensional arrangement naturally reduces the need for complex broadcast and load schemes required in planar designs.
Solution Approach 2:
The patent divides the fuse array into multiple separate stacked layers rather than using a single planar layer. This segmentation into first and second fuse array layers, with fuse circuitry positioned between them, creates physically separated fuse structures. This spatial separation reduces the impact of soft errors, as errors affecting one layer are less likely to propagate to other layers, thereby improving overall reliability.
Data Source
AI summary
Apparatuses, methods, and computing systems relating to three-dimensional fuse architectures are disclosed. An apparatus includes a semiconductor substrate, a fuse array on or in the semiconductor substrate, and fuse circuitry on or in the semiconductor substrate. The fuse array includes fuse cells. The fuse circuitry is configured to access the fuse cells. The fuse circuitry is offset from the fuse array such that the fuse circuitry is disposed between the semiconductor substrate and the fuse array, or the fuse array is disposed between the semiconductor substrate and the fuse circuitry.