3D GAA Memory Structure for Short-Channel Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit manufacturing is to reduce device linewidth and increase memory density while addressing issues like leakage current, capacitance, and short channel effects, which are limitations in current semiconductor structures.
Innovation Solution
A semiconductor structure and manufacturing method involving a base with active pillars, bit lines, word lines, isolation layers, and memory structures are formed, where the word line surrounds the channel region, and memory structures are stacked between isolation layers, enabling 3D semiconductor devices with improved integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the device linewidth is reduced to improve integration degree, then the memory density increases, but the short channel effects and leakage current worsen
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional GAA structures where the channel extends vertically. Multiple channel regions are stacked in the vertical dimension, allowing continued scaling in the plane while maintaining adequate channel length control through the vertical stacking approach. This dimensional transition enables higher density while preserving electrical performance.
Solution Approach 2:
The gate structure completely surrounds the channel region in a nested configuration, with the gate wrapping around the channel from all sides. This nested gate-all-around structure provides superior electrostatic control over the channel compared to planar gates, effectively suppressing short channel effects while enabling smaller device footprints and higher integration density.
2Device complexity
If the device linewidth is reduced to increase integration degree, then more devices fit in the same area, but the gate control performance deteriorates
Solution Approach 1:
The gate structure completely surrounds the channel region in a nested configuration, with the gate wrapping around the channel from all sides. This nested gate-all-around structure provides superior electrostatic control over the channel compared to planar gates, effectively suppressing short channel effects while enabling smaller device footprints and higher integration density.
Solution Approach 2:
The patent transitions from planar 2D transistor structures to three-dimensional GAA structures where the channel extends vertically. Multiple channel regions are stacked in the vertical dimension, allowing continued scaling in the plane while maintaining adequate channel length control through the vertical stacking approach. This dimensional transition enables higher density while preserving electrical performance.
3Quantity of substance
If the memory device size is reduced to increase density, then the storage capacity per area increases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional GAA structures where the channel extends vertically. Multiple channel regions are stacked in the vertical dimension, allowing continued scaling in the plane while maintaining adequate channel length control through the vertical stacking approach. This dimensional transition enables higher density while preserving electrical performance.
Solution Approach 2:
The channel region is segmented into multiple discrete segments stacked vertically, with each segment forming part of the overall channel path. This segmentation into stacked channels allows the device to achieve equivalent electrical performance to longer planar channels while occupying smaller planar area, thereby enabling higher density with relaxed linewidth precision requirements.
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; a bit line; a word line; an active pillar, wherein the active pillar includes a source region, a channel region, and a drain region, the bit line is connected to one of the source region and the drain region of the active pillar, and the word line surrounds the channel region of the active pillar; a plurality of memory structures, wherein the memory structure is located between adjacent isolation layers, the memory structure includes a first electrode plate, a medium layer, and a second electrode plate that are sequentially stacked, the medium layer is located between the first electrode plate and the second electrode plate, the first electrode plate is connected to the other of the source region and the drain region of the active pillar.