3D Lateral Gate-All-Around Transistor Stacking for Higher Integration
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Solution Overview
Problem
Lateral gate-all-around transistors face challenges in achieving high integration levels due to limitations in semiconductor technology, including mechanical strength issues with silicon nanowires and compatibility problems in multilayer structures, which hinder their advancement as next-generation integrated circuit devices.
Innovation Solution
A three-dimensional integrated circuit structure is developed by superimposing multiple layers of lateral gate-all-around transistors vertically, isolated by an insulating layer, with channels of the same type and design, allowing for parallel and equal-length channels, and a manufacturing method that includes specific steps for forming and connecting these transistors to enhance integration and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If nanosheets are used as channels to increase transmission current, then the channel transmission capability is improved, but the device area increases which reduces integration level
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional vertically superimposed structures. Multiple layers of lateral gate-all-around transistors are stacked in the vertical direction, allowing the device to utilize the third dimension (height) for increasing integration density while maintaining compact footprints in the planar area. This dimensional transition resolves the contradiction by enabling high transmission current through multiple stacked channels without proportionally increasing the device area.
Solution Approach 2:
The patent divides the transistor channel into multiple discrete layers, with each layer containing lateral gate-all-around transistors with nanosheet channels. These segmented layers are vertically stacked and electrically isolated by insulating layers, allowing independent optimization of each layer's transmission characteristics while achieving cumulative current capability across all layers without requiring a single large-area device.
2Productivity
If vertically superimposed multilayer structures are formed, then integration level is improved, but process compatibility and manufacturing complexity increase
Solution Approach 1:
The patent employs preliminary patterning and sacrificial layer formation before final transistor assembly. Insulating layers are pre-formed between channels, and sacrificial structures are placed in advance to guide subsequent self-aligned etching and material deposition. This preliminary action simplifies the manufacturing of complex vertically superimposed structures by establishing alignment references and isolation structures before the critical transistor formation steps.
Solution Approach 2:
The patent implements a nested structure where lateral gates wrap around nanosheet channels in a gate-all-around configuration, and multiple such nested units are vertically stacked. Each transistor layer is self-contained with its gate completely surrounding its channel, and these nested transistor units are nested within a vertically stacked architecture with shared source/drain regions, reducing overall structural complexity while achieving high integration.
3Reliability
If lateral gate-all-around transistors are used, then gate control on channel is maximized, but short-channel effects and energy consumption issues arise at reduced sizes
Solution Approach 1:
The patent uses nanosheets as channel materials, which provide superior mechanical strength and electrical characteristics compared to conventional materials. The nanosheet channels are combined with high-k dielectric gate insulators and metal gates to form a composite structure that enhances gate control efficiency. This composite material approach enables effective control of ultra-short channels while reducing leakage current and energy consumption through the superior material properties.
Solution Approach 2:
The lateral gate-all-around structure completely surrounds the nanosheet channel in three dimensions, providing maximum gate control from all directions (top, bottom, and sides). This three-dimensional gating approach, combined with vertical stacking of multiple layers, achieves exceptional control over channel current with minimal channel length, thereby suppressing short-channel effects and reducing the energy required to switch the transistor while maintaining high transmission capability.
Data Source
AI summary
Vertically superimposed lateral gate-all-around metal-oxide-semiconductor field-effect transistors are provided, a structure of a novel three-dimensional integrated circuit such as a CMOS logic circuit that is composed of the vertically superimposed lateral gate-all-around transistors, a random-access memory and the like, and a manufacturing method for the novel three-dimensional integrated circuit are provided. The manufacturing method for the vertically superimposed lateral gate-all-around transistors includes: first preparing a monolayer channel and a source/drain, then protected with a sacrificial layer; preparing an insulating isolation layer, preparing above repeated structures on the insulating isolation layer; preparing an insulating spacer layer between the source/drain and a gate of each of the layers, a gate oxide, a gate, and a source/drain electrode in a unified manner, and finally preparing a connecting wire connected to the outside. The novel three-dimensional integrated circuit can be implemented by connecting the lateral gate-all-around transistors by means of a wire.