3D Gain-Cell Memory Stack for Higher Storage Density
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing storage capacity per unit area, particularly in achieving a novel structure for stacking memory cells to enhance storage density.
Innovation Solution
A semiconductor device is designed with a configuration of stacked memory cells, each comprising transistors and capacitors, where the gate of one transistor is connected to the source or drain of another, and a semiconductor filling a hole penetrates wiring and electrodes, with insulating films maintaining conductivity and hydrogen release properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked to increase storage capacity per unit area, then storage density is improved, but device structure complexity increases
Solution Approach 1:
The patent implements vertical stacking of memory cells in the third dimension, transitioning from planar two-dimensional layout to three-dimensional architecture. Multiple memory cells are stacked above each other, with each cell containing transistors and capacitors arranged vertically, thereby increasing storage capacity per unit area while managing structural complexity through systematic vertical integration
Solution Approach 2:
The patent employs nested configuration where transistors are embedded within insulating films, and memory cells are stacked within a unified device structure. The semiconductor layers, insulating films, and conductive elements are nested in multiple hierarchical levels, allowing compact integration of multiple functional components within each vertical stack
2Reliability
If transistors with metal oxide semiconductor layers are used, then data retention is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes metal oxide semiconductor layers with specific compositional parameters (such as In-Ga-Zn-O with controlled atomic ratios) to achieve desired electrical characteristics. By adjusting the metal element ratios and oxidation states, the semiconductor layer exhibits appropriate carrier concentration and mobility, enabling reliable data retention while accommodating manufacturing variations
Solution Approach 2:
The patent employs composite semiconductor structures combining metal oxide layers with other materials. The metal oxide semiconductor layer is integrated with insulating films and conductive layers to form a composite device structure that leverages the complementary properties of each material, achieving both data retention reliability and manufacturability
Data Source
AI summary
A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.