3D GaN IC Die Stacking to Cut Back-Gating and Parasitic Inductance
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Solution Overview
Problem
Gallium nitride (GaN) semiconductor devices face challenges with back-gating effects due to the lack of n/p junctions, leading to reduced switching performance, and existing solutions like discrete transistors with wire bonding result in high parasitic inductance and large area occupation.
Innovation Solution
A 3D semiconductor structure is proposed, where high-side and low-side transistors are on separate IC dies, vertically stacked and bonded through a conductive adhesive layer, avoiding wire bonding and reducing parasitic inductance by using GaN-on-silicon-on-insulator substrates with deep trench isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete transistors with wire bonding are used to isolate high-side and low-side transistors, then switching performance is improved, but parasitic inductance increases and area occupation increases
Solution Approach 1:
The patent transitions from planar wire bonding to vertical 3D stacking, moving the isolation mechanism from a 2D plane to a 3D vertical architecture. High-side and low-side transistors are placed on separate stacked substrates, eliminating the need for lateral wire bonds and reducing parasitic inductance while maintaining electrical isolation.
Solution Approach 2:
The patent divides the semiconductor device into multiple independent substrates (first substrate for high-side transistor, second substrate for low-side transistor), with each substrate being electrically isolated. This segmentation allows independent optimization of each transistor while eliminating mutual interference and reducing parasitic effects.
2Reliability
If discrete transistors with wire bonding are used to isolate high-side and low-side transistors, then switching performance is improved, but area occupation increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking substrates, converting a planar area-consuming layout into a compact 3D structure. This vertical integration dramatically reduces the footprint area while maintaining the functional isolation between high-side and low-side transistors.
Solution Approach 2:
The patent merges multiple functional components (high-side transistor, low-side transistor, isolation structures, interconnects) into a single integrated 3D stacked package, eliminating the need for separate discrete components and wire bonding, thereby reducing overall area occupation.
3Adaptability or versatility
If GaN semiconductor devices are used instead of silicon-based devices, then operation at high frequencies, high voltages, and high temperatures is enabled, but back-gating effects reduce switching performance
Solution Approach 1:
The patent segments the GaN device into electrically isolated substrates, preventing back-gating effects by ensuring that the substrate cannot act as a common back gate for both high-side and low-side transistors. Each GaN device operates independently on its own substrate, maintaining the high-frequency and high-voltage advantages of GaN while eliminating the back-gating drawback.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a three-dimensional (3D) semiconductor structure for wide-bandgap semiconductor devices in which the wide-bandgap semiconductor devices are split amongst a first IC die and a second IC die. The first IC die includes a first substrate and a first semiconductor device. The first substrate includes a first wide-bandgap material, and the first semiconductor device overlies the first substrate and is formed in part by the first wide-bandgap material. The second IC die overlies the first IC die and is bonded to the first IC die by a bond structure between the first and second IC dies. Further, the second IC die includes a second substrate and a second semiconductor device. The second substrate includes a second wide-bandgap material, and the second semiconductor device underlies the second substrate and is formed in part by the second wide-bandgap material.


