3D Gate Structure Contact Plug Layout for Reliable Layer Connections
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to enhance the degree of integration and operational reliability, particularly as the two-dimensional approach reaches its limits, necessitating innovative three-dimensional stacking of memory cells while maintaining stable and efficient manufacturing processes.
Innovation Solution
The semiconductor device employs a structure with alternately stacked conductive and insulating layers, featuring multiple gate structures and contact plugs with inflection portions, allowing for precise electrical connections and improved integration by extending contact plugs through multiple gate layers, and a manufacturing method that involves forming and replacing material layers to achieve efficient stacking and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are extended through multiple gate structures to improve electrical connectivity, then manufacturing precision requirements increase
Solution Approach 1:
The patent forms opening patterns and contact plug patterns at preliminary stages before the gate structures are fully formed. The opening patterns are formed through the second gate structure to expose portions of the first gate structure, and contact plugs are subsequently formed in these pre-prepared openings. This preliminary action ensures precise positioning and reduces manufacturing complexity.
2Productivity
If multiple gate structures are stacked to increase integration density, then device complexity increases
Solution Approach 1:
The patent divides the gate structure into multiple distinct gate structures (first gate structure, second gate structure, third gate structure) that are stacked vertically. Each gate structure contains alternating conductive layers and insulating layers, creating segmented functional units. This segmentation allows for independent formation and control of each gate structure while achieving high integration density through vertical stacking.
Solution Approach 2:
The patent transitions from two-dimensional planar structures to three-dimensional vertical stacking by forming multiple gate structures stacked in the vertical direction. The first, second, and third gate structures are arranged vertically, with contact plugs extending through multiple layers to connect conductive layers at different heights, effectively utilizing the vertical dimension to increase integration density.
3Reliability
If contact plugs include inflection portions at gate structure interfaces to improve connection stability, then manufacturing process complexity increases
Solution Approach 1:
The patent forms opening patterns that extend through the second gate structure to expose portions of the first gate structure before the third gate structure is formed. Contact plugs are then formed in these pre-formed openings, creating inflection portions at the interfaces between gate structures. This preliminary formation of openings simplifies the subsequent manufacturing steps compared to forming complex inflected structures in a single step.
Data Source
AI summary
A semiconductor device may include: a first gate structure including a plurality of first conductive layers that are alternately stacked with a plurality of first insulating layers; a second gate structure including a plurality of second conductive layers that are alternately stacked with a plurality of second insulating layers; a third gate structure including third conductive layers that are alternately stacked with a plurality of third insulating layers; and a first contact plug extending into the first gate structure through the third gate structure and the second gate structure, the first contact plug connected to a first of the plurality of first conductive layers, and the first contact plug including a first inflection portion located at an interface between the second gate structure and the third gate structure.