3D Gate Contact Layout for Lower RC Delay in Memory Arrays
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Solution Overview
Problem
As the number of layers in multilayer semiconductor memory structures increases, the wiring length becomes longer, leading to deteriorated electrical performance, particularly in terms of RC delay.
Innovation Solution
The semiconductor memory device incorporates a design with first and second gate electrodes and a contact extending in specific directions, along with a contact region and peripheral circuit structure, which includes a wordline driver connected through a contact plug to reduce wiring length and improve RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in multilayer structure is increased to increase integration, then the integration capacity is improved, but the wiring length becomes longer which deteriorates electrical performance
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring by extending gate electrodes and contacts in the vertical direction (third direction). Multiple gate electrodes are stacked vertically and connected through vertical contacts, allowing signals to traverse shorter distances in 3D space rather than following extended planar paths, thereby reducing wiring length while maintaining high integration capacity.
2Quantity of substance
If the number of layers in multilayer structure is increased, then the integration capacity is improved, but the RC delay deteriorates due to longer wiring
Solution Approach 1:
By implementing vertical stacking of gate electrodes and contacts in the third direction, the patent creates direct vertical signal paths that significantly reduce the length of conductive lines. This dimensional transition reduces both resistance (shorter paths) and capacitance (reduced overlap area), thereby decreasing RC delay while achieving high integration capacity through vertical layering.
3Ease of operation
If stepped wiring structure is used to control multilayer structure, then the layer control is improved, but the wiring length becomes longer which deteriorates electrical performance
Solution Approach 1:
The patent replaces the stepped wiring approach with a vertical stacking architecture where gate electrodes and contacts are arranged in the third direction. This eliminates the need for stepped lateral extensions, providing simplified layer control through vertical positioning while simultaneously reducing wiring length by utilizing the vertical dimension for direct signal routing.
Data Source
AI summary
An example semiconductor memory device may include a first conductive line extending in a first direction perpendicular to a substrate, a first gate electrode extending in a second direction, crossing the first direction, on the substrate, a first semiconductor pattern extending from the first conductive line to the first gate electrode, a second gate electrode spaced apart from the first gate electrode on the substrate and extending in the second direction, and a contact extending in the first direction and electrically connected with the first gate electrode and the second gate electrode.