3D Gate Structures With Horizontal Extensions For Memory Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional memory devices experience high resistance in semiconductor lines passing through SSL gate structures and ground select lines, degrading their performance.
Innovation Solution
The implementation of extended gate structures with vertical and horizontal portions over stacks of semiconductor lines, where the horizontal extension portions are recessed between the semiconductor lines, reducing resistance by forming an inversion layer with lower resistance when voltage is applied.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional vertical gate structures are used, then the device layout is simple, but the resistance of semiconductor lines is high which degrades performance
Solution Approach 1:
The gate structure is extended from a purely vertical configuration to include horizontal portions that protrude between semiconductor lines. This dimensional extension allows the gate to interact with semiconductor lines at multiple locations simultaneously, reducing resistance without complicating the overall device layout.
Solution Approach 2:
The gate structure is divided into multiple segments: a vertical portion and one or more horizontal extension portions. Each segment serves a specific function in reducing resistance at different locations along the semiconductor lines, allowing the gate to effectively control multiple lines without increasing overall complexity.
2Reliability
If the gate structure is extended to reduce resistance, then the inversion region length increases, but the manufacturing process becomes more complex
Solution Approach 1:
The horizontal extension portions are formed as an integrated part of the vertical gate structure using a unified material layer and formation process. This merging approach allows the extended gate to be manufactured in the same process steps as traditional gates, minimizing additional manufacturing complexity while achieving the resistance reduction benefit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the resistance of semiconductor lines, enhancing the performance of three-dimensional memory devices by increasing the length of the inversion region along the semiconductor lines without compromising memory array layout efficiency.
Implementation Method 1
forming an inversion layer with lower resistance when voltage is applied
Data Source
AI summary
A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure.