3D Gate Structure for NAND Flash Memory Current Stability
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Solution Overview
Problem
As the integration of NAND flash memory increases, there is a challenge in maintaining NAND cell current, as cell structure changes over time lead to decreased current flow areas in source and drain regions, resulting in potential erase-failure and reduced reliability.
Innovation Solution
A three-dimensional gate structure with a U-shaped tunnel oxide layer and floating gate is implemented, where the tunnel oxide and floating gate are partially positioned below the source/drain regions, enhancing current-carrying capacity and stability through a fabrication process involving trench formation, etching, and deposition of oxide-nitride-oxide layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of NAND flash memory is increased, then storage capacity is improved, but cell current decreases due to reduced current flow areas in source and drain regions
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional gate structure that extends vertically into the substrate. This dimensional change increases the gate surface area without increasing the planar footprint, thereby maintaining cell current while enabling higher integration density. The 3D gate structure comprises a gate trench extending below the substrate surface with gate material filling the trench, creating additional gate area in the vertical dimension.
2Quantity of substance
If the degree of integration of NAND flash memory is increased, then storage capacity is improved, but cell structure changes lead to decreased current flow areas
Solution Approach 1:
The gate structure extends vertically below the substrate surface into a gate trench, utilizing the third dimension to increase gate area. This vertical extension provides additional gate surface area that compensates for the reduction in planar current flow areas caused by higher integration density, maintaining adequate current flow paths.
3Reliability
If a three-dimensional gate structure is implemented, then cell current is maintained or increased, but device complexity increases
Solution Approach 1:
The gate structure is segmented into distinct components: a gate trench extending into the substrate, gate material filling the trench, and source/drain regions positioned adjacent to the gate. This segmentation allows each component to be optimized independently while working together to maintain cell current. The segmented structure also facilitates systematic fabrication processes.
Solution Approach 2:
The patent applies different materials and structures to different regions: the gate trench is filled with conductive gate material, the substrate contains doped source/drain regions, and tunnel oxide layers are formed in specific locations. This local differentiation optimizes the function of each region while managing overall device complexity through targeted structural modifications.
Data Source
AI summary
Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.