3D Stacked Gate Structure With Thickened Pads for Reliable Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration, reliability, and durability, particularly in three-dimensional configurations where the demand for improved performance and efficiency is increasing.
Innovation Solution
A three-dimensional semiconductor device is designed with a substrate having distinct areas and gate electrodes that include extension portions and pad portions, along with separation patterns and contact plugs, forming stacked gate groups and penetration structures to enhance integration and reliability. The method involves forming a mold structure with interlayer insulating and sacrificial layers, patterning, and substituting sacrificial layers with gates and separation patterns to create a robust semiconductor architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional semiconductor devices are designed to increase integration density, then the degree of integration is improved, but reliability and durability deteriorate due to increased structural complexity and stress
Solution Approach 1:
The gate electrode is segmented into multiple portions (first gate electrode portion, second gate electrode portion, third gate electrode portion) with different thicknesses. This segmentation allows each portion to be optimized for specific functions, reducing overall stress while maintaining high integration density in the three-dimensional structure.
Solution Approach 2:
Different portions of the gate electrode are assigned different local qualities (thicknesses) based on their specific functional requirements. The first gate electrode portion has a first thickness, the second has a second thickness greater than the first, and the third has a third thickness greater than the second. This local quality variation optimizes both integration density and reliability by addressing stress and electrical requirements at different locations.
2Ease of manufacture
If gate electrodes are made with uniform thickness to simplify manufacturing, then ease of manufacture is improved, but electrical performance and reliability deteriorate due to inability to optimize for different functional regions
Solution Approach 1:
The gate electrode structure implements local quality by varying the thickness of different gate electrode portions according to their specific functional requirements. This allows optimization of electrical performance in different regions while maintaining a systematic manufacturing approach through the defined multi-layer structure.
Solution Approach 2:
The solution transitions from a two-dimensional uniform thickness concept to a three-dimensional variable thickness structure. The gate electrode portions are arranged in a vertical stack with different thicknesses, utilizing the third dimension to achieve both manufacturing feasibility and electrical performance optimization.
3Reliability
If separation patterns are added to improve structural integrity, then reliability is improved, but device complexity increases due to additional manufacturing steps and structures
Solution Approach 1:
The separation pattern is merged with the gate electrode structure by positioning it to overlap with at least a portion of the gate electrode. This integration reduces the need for completely separate manufacturing steps for both the gate electrode and separation pattern, thereby reducing overall device complexity while maintaining structural integrity and reliability.
Data Source
AI summary
A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.