3D Memory Fabrication with Gate Slit Bonding and Substrate Removal
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Solution Overview
Problem
The demand for increased memory capacity, driven by AI, big data, and IoT, has reached a limit with planar NAND memory cells, as feature sizes approach a lower limit, making 3D NAND memory architecture necessary to address density limitations and scalability challenges.
Innovation Solution
A method for forming a 3D memory device involves creating a stack structure on a substrate, forming gate line slit structures, bonding a periphery circuit to the memory array, and removing portions of the substrate to create a supplemental semiconductor layer, enabling vertical integration and increased memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar NAND memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) NAND memory cell architecture to three-dimensional (3D) vertical stacking architecture. Memory cells are arranged in vertical columns extending through multiple stacked layers, enabling significant increases in memory density without requiring further reduction of feature sizes. This dimensional change allows continued scaling while avoiding the manufacturing complexity and cost penalties associated with extreme planar scaling.
2Quantity of substance
If feature sizes of memory cells are reduced to increase density, then memory capacity is improved, but process fabrication becomes challenging and costly
Solution Approach 1:
The invention employs vertical stacking of memory cell layers to achieve higher capacity without reducing lateral feature sizes. The fabrication process forms three-dimensional structures where memory cells extend vertically through multiple layers, allowing standard planar fabrication techniques to be used for each layer while achieving increased capacity through the third dimension.
Solution Approach 2:
The memory device is divided into multiple stacked layers, each containing memory cells arranged in vertical columns. This segmentation allows the fabrication process to be broken down into manageable stages, with each layer being formed using established processes, thereby maintaining fabrication ease while achieving high capacity through the cumulative effect of multiple layers.
3Area of stationary object
If planar memory cell scaling continues, then memory density approaches upper limit, but device area reduction is achieved
Solution Approach 1:
The patent achieves high memory density within a reduced chip area by transitioning to vertical stacking architecture. Memory cells are arranged in three-dimensional columns that extend vertically through multiple stacked layers, allowing significantly more storage capacity to be packed into a smaller lateral footprint compared to planar arrangements.
Data Source
AI summary
Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a method for forming a 3D memory device can comprise forming a first semiconductor structure, comprising forming a stack structure on a first substrate, and forming a gate line slit structure including a filling structure penetrating the stack structure and extending into the first substrate. The method can further comprise forming a second semiconductor structure including a periphery circuit on a second substrate, and bonding the second semiconductor structure to the first semiconductor structure. The method can further comprise removing a portion of the first substrate and a portion of the gate line slit structure extended into the first substrate, and forming a supplemental semiconductor layer on a remaining portion of the first substrate.