3D Gate-Stack Through-Region Layout for Reliable Staircase Connections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the number of stacked gate electrodes in semiconductor devices increases, the difficulty in electrically connecting them to peripheral circuits also increases, leading to defects and reduced integration efficiency.
Innovation Solution
A three-dimensional semiconductor device design that includes a gate-stacked structure with through regions passing through the gate-stacked structure, featuring a staircase shape and stepped portions to facilitate electrical connections between gate electrodes and peripheral circuits, thereby enhancing integration and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked gate electrodes is increased to achieve high degree of integration, then integration density is improved, but the difficulty of electrical connection to peripheral circuits increases
Solution Approach 1:
The through region extends vertically through multiple stacked gate electrodes in the third dimension, enabling electrical connections to be established from the substrate level through the stack to the upper substrate, thereby simplifying the connection process despite increased integration density
Solution Approach 2:
The through region is divided into multiple sections with different widths - a lower region and an upper region wider than the lower region - allowing the structure to accommodate multiple conductive plugs at different levels while maintaining proper spacing and electrical isolation between adjacent connections
2Quantity of substance
If the number of stacked gate electrodes is increased, then integration density is improved, but defects increase due to connection difficulties
Solution Approach 1:
By utilizing the vertical dimension to pass through regions through the entire gate stack, the design provides reliable electrical pathways that reduce connection defects even as the number of stacked electrodes increases
Solution Approach 2:
The through region acts as an intermediary structure that facilitates reliable electrical connection between the substrate and upper substrate, reducing defects by providing a dedicated pathway that is independent of the increased number of gate electrodes
Data Source
AI summary
A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.