3D Nonvolatile Memory Gate Stack Support for Low-Resistance Electrodes
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Solution Overview
Problem
Existing three-dimensional nonvolatile memory devices face challenges in reducing the resistance of gate electrodes and preventing process defects, which affect the operation speed and reliability of the devices.
Innovation Solution
The proposed solution involves a three-dimensional nonvolatile memory device structure where gate electrodes are stacked with an interlayer dielectric and supporters are used to reduce the resistance and prevent defects. The supporters, made of dielectric or semiconductor material, penetrate the gate electrodes and maintain the spacing between interlayer dielectrics, preventing collapse during wet etch processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate electrodes are made thinner to increase integration density, then device integration is improved, but gate electrode resistance increases
Solution Approach 1:
The gate electrode uses a composite structure comprising a first conductive layer (e.g., polysilicon) and a second conductive layer (e.g., metal material such as aluminum or copper) stacked in sequence. This composite material approach allows the thin gate electrode to maintain low resistance while achieving high integration density, as the metal layer provides superior electrical conductivity compared to traditional single-material polysilicon gates.
2Ease of manufacture
If interlayer dielectric layers are removed to form openings, then manufacturing process is simplified, but dielectric layers collapse during wet etch process
Solution Approach 1:
A support structure is formed in advance within the interlayer dielectric layers before the openings are etched. This preliminary structural reinforcement prevents the dielectric layers from collapsing during the wet etch process, enabling safe removal of dielectric material to form openings while maintaining structural integrity throughout the fabrication process.
Solution Approach 2:
The support structure acts as an intermediary element that maintains the spacing between interlayer dielectric layers during the wet etch process. This mediator prevents direct contact and potential collapse of the dielectric layers, allowing the etching process to proceed without structural failure.
3Productivity
If gate electrode area is reduced to increase cell density, then integration is improved, but operation speed decreases
Solution Approach 1:
By incorporating a metal conductive layer in the composite gate electrode structure, the electrical conductivity is significantly enhanced. This allows the gate electrode to maintain a smaller area for higher cell density while the improved conductivity compensates for the reduced area, thereby maintaining or even improving operation speed despite the smaller gate footprint.
Data Source
AI summary
A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.