3D Grid Interconnection Structure for Low-Parasitic Semiconductor Routing
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Solution Overview
Problem
The challenge lies in creating an interconnection structure between device layers in semiconductor technology that reduces parasitic resistance and capacitance, while being compatible with the device integration process, which is difficult due to incompatibility between interconnection and device integration processes.
Innovation Solution
An interconnection structure is developed with alternately stacked via layers and interconnection layers, where via holes and conductive nodes are arranged to provide conductive channels, allowing for electrical connections between layers, and the layout resembles a 3D grid structure to facilitate routing and reduce parasitic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If an interconnection structure is introduced to reduce parasitic resistance and capacitance, then RC delay and power consumption are reduced, but the process compatibility with device integration becomes difficult
Solution Approach 1:
The patent combines the interconnection structure formation with the device integration process by using the same sacrificial layer stack for both device active regions and interconnection via holes. The grid pattern formation, etching, and material deposition steps are merged into a unified process flow that simultaneously creates both device and interconnection structures, eliminating the need for separate interconnection processing steps.
Solution Approach 2:
The sacrificial layer stack serves multiple functions: it defines both device active regions and interconnection via hole positions, provides a grid pattern for both device and interconnection structures, and enables subsequent formation of both semiconductor devices and conductive interconnections through the same structural framework. This multi-functional approach ensures process compatibility while achieving low parasitic interconnections.
2Speed
If an interconnection structure is introduced to reduce parasitic resistance and capacitance, then RC delay is reduced, but the process compatibility with device integration becomes difficult
Solution Approach 1:
The patent merges interconnection structure formation with device integration by using identical process steps for both. The grid pattern definition, sacrificial layer removal, and conductive material deposition are performed in a unified process that simultaneously creates low-parasitic interconnections and device structures, achieving fast signal propagation without process incompatibility.
Solution Approach 2:
The sacrificial layer stack is formed beforehand with a predetermined grid pattern that defines both device active regions and interconnection via hole positions. This preliminary structuring enables subsequent process steps to simultaneously create both device and interconnection features, reducing RC delay while maintaining process compatibility through pre-planned integration.
3Quantity of substance
If an interconnection structure with via layers and interconnection layers is created, then integration density is increased, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of multiple interconnection layers with device structure creation by using the same sacrificial layer stack and grid pattern formation process. The alternating via layers and interconnection layers are created through unified etching and deposition steps that simultaneously define both interconnection and device features, increasing integration density without proportionally increasing process complexity.
Solution Approach 2:
The interconnection structure is segmented into alternating via layers and interconnection layers, each formed through systematic repetition of etching and deposition steps. This segmented approach allows incremental building of complex three-dimensional interconnection networks while maintaining manageable process complexity through modular, repeatable manufacturing steps.
Data Source
AI summary
An interconnection structure for semiconductor devices formed on a substrate may be arranged under the semiconductor devices. The interconnection structure includes at least one via layer and at least one interconnection layer alternately arranged in a direction from the semiconductor device to the substrate, wherein each via layer includes via holes respectively arranged under at least a part of the semiconductor devices, and each interconnection layer includes conductive nodes respectively arranged under at least a part of the semiconductor devices, and in a same interconnection layer, a conductive channel is provided between at least one conductive node and at least another node; and the via holes in each via layer and the conductive nodes in each interconnection layer corresponding to the via holes at least partially overlap with each other in the direction from the semiconductor device to the substrate.