3D Half-Flash Structure for Faster Programming and Erasing
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Solution Overview
Problem
Conventional flash memory devices have a lower coupling ratio due to the resistance associated with the polysilicon control gate electrode, leading to slower programming and erasing times.
Innovation Solution
The implementation of a flash memory device with a three-dimensional half-flash structure, where the control gate electrode is shorter in length than the floating gate electrode, and additional electrical contacts are provided to the gate dielectric layer for programming and erasing, thereby avoiding the resistance associated with the polysilicon control gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional flash memory structure with polysilicon control gate electrode is used, then the device structure is simple and easy to manufacture, but the resistance associated with the polysilicon control gate electrode results in a lower coupling ratio and slower programming and erasing times
Solution Approach 1:
The patent transitions from a conventional planar flash memory structure to a three-dimensional half-flash structure. The control gate electrode is positioned only over the drain region rather than spanning the entire channel length, creating a vertical stacking configuration where the control gate, floating gate, tunnel dielectric, and channel are arranged in multiple layers. This dimensional change increases the coupling ratio between control gate and floating gate, thereby improving programming and erasing speed despite the increased structural complexity.
Solution Approach 2:
The control gate electrode is segmented into discrete regions corresponding to individual memory cells or cell groups, rather than forming a continuous gate across the entire device. Each control gate electrode is positioned over its respective drain region and forms a stacked structure with the floating gate and tunnel dielectric. This segmentation allows for independent control of different memory cell regions and improves the coupling ratio by concentrating the control gate field where it is most effective.
2Loss of time
If additional electrical contacts are provided to the gate dielectric layer for programming and erasing, then the coupling ratio increases and programming/erasing times decrease, but the device structure becomes more complex
Solution Approach 1:
The patent extracts the programming and erasing functionality from the conventional control gate electrode path and creates dedicated electrical contact paths through the gate dielectric layer. These additional electrical contacts provide direct access to the floating gate and control gate, enabling efficient charge injection and removal without having to route signals through the polysilicon control gate electrode. This extraction of the programming path reduces the effective resistance and improves programming/erasing speed despite adding structural elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a higher coupling ratio, leading to faster programming and erasing times for the flash memory device, while also reducing the resistance associated with the polysilicon control gate electrode.
Implementation Method 1
a tunnel dielectric layer located between the channel and the floating gate electrode
Implementation Method 2
a gate dielectric layer located between the floating gate electrode and the control gate electrode
Implementation Method 3
The coupling ratio of a flash memory cell may be defined as the ratio of the capacitance between the control gate and the floating gate CONO to the sum of the capacitances
Data Source
AI summary
A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.