Epitaxial 3D Horizontal Nanosheets With High-Mobility 2D Channels
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Solution Overview
Problem
Conventional semiconductor device fabrication techniques are limited by their two-dimensional nature, which restricts transistor complexity and dimensionality, approaching physical atomic limitations with single-digit nanometer semiconductor device fabrication nodes.
Innovation Solution
The proposed solution involves the use of 2D materials integrated with nano sheet masks to form semiconductor devices with increased transistor density in volume rather than area, enabling sub-nanometer channel thickness regions and future nanoscale transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 2D fabrication techniques are used, then manufacturing simplicity is maintained, but transistor density and device complexity are limited
Solution Approach 1:
The patent transitions from conventional 2D planar fabrication to 3D vertical fabrication by stacking multiple semiconductor layers vertically. This dimensional change enables increased transistor density within the same footprint area, as transistors are arranged in multiple levels rather than a single plane, directly resolving the contradiction between maintaining manufacturing simplicity and increasing transistor density.
Solution Approach 2:
The patent implements nested structures where gate electrodes, dielectric layers, and semiconductor layers are stacked within each other vertically. Each layer is positioned within the spatial envelope of the layers below it, creating a nested configuration that maximizes transistor density while maintaining a compact overall structure.
2Productivity
If 2D materials are used to increase transistor density in volume, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the semiconductor device into distinct functional layers including semiconductor layers, dielectric layers, and gate electrodes, with each layer having a specific thickness and position. This segmentation allows for precise control of each individual layer's dimensions and properties, enabling high transistor density while maintaining manufacturing precision through layer-by-layer fabrication control.
Solution Approach 2:
The patent utilizes 2D materials with specifically tuned physical and electrical parameters to achieve high transistor density. By changing material parameters such as carrier mobility, bandgap, and thickness at the nanometer scale, the device achieves enhanced performance and density while the precise control of these parameters through advanced material synthesis techniques maintains manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of semiconductor devices with enhanced performance and increased complexity, enabling the development of advanced logical circuits such as CPUs, GPUs, and FPGAs.
Implementation Method 1
Such 2D materials have the potential for very high mobility, and therefore enable sub-nanometer channel thickness regions
Data Source
AI summary
Methods for the manufacture of semiconductor devices constructed with three-dimensional (3D) horizontal nano sheets with high mobility two-dimensional (2D) material channels are disclosed. Aspects can include forming a semiconductor material; selectively forming a seed material around the bridge; selectively forming a two-dimensional (2D) material around the seed material; forming an active gate around a central portion of the 2D material thereby exposing end portions of the 2D material; and growing source/drain structures coupled to the end portions of the 2D material, respectively.