3D Hybrid Memory With Conductive Oxide Channels for Dense Stacking
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Solution Overview
Problem
Existing semiconductor device fabrication faces challenges in scaling beyond single digit nanometer nodes, particularly in transitioning from 2D to 3D integration for logic chips and DRAM, where vertical stacking of transistors is difficult to implement effectively.
Innovation Solution
The development of non-planar, 3D structures with vertically stacked transistors, utilizing conductive dielectric channels and Gate All Around (GAA) structures, which include semiconductor and conductive oxide-based nanosheets, allowing for higher transistor density and integration of DRAM cells with reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2D transistor fabrication is used, then manufacturing process is simpler, but transistor density per unit area cannot be increased beyond scaling limits
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D vertically stacked transistors, increasing transistor density by utilizing the vertical dimension. Multiple transistor layers are stacked above each other on the substrate, allowing significantly more transistors per unit area while managing fabrication complexity through systematic process design.
Solution Approach 2:
The patent implements nested structures where conductive oxide nanosheets are embedded within semiconductor layers, and multiple transistor layers are stacked within a vertical column structure. This nesting approach maximizes space utilization and increases transistor density without proportionally increasing fabrication complexity.
2Quantity of substance
If vertical stacking of transistors is implemented, then transistor density in volume increases, but leakage current increases
Solution Approach 1:
The patent uses different materials with specific properties for different regions: conductive oxide nanosheets (InGaZnO, In2O3, SnO2) are used for channel regions requiring low leakage, while semiconductor materials form other structural regions. This local material optimization reduces leakage current in the vertical stacked structure while maintaining high transistor density.
Solution Approach 2:
The patent employs composite structures combining conductive oxide nanosheets with semiconductor materials and dielectric layers. This composite approach creates vertically stacked transistors with optimized electrical properties, reducing leakage current through the unique properties of conductive oxides while maintaining high density.
3Quantity of substance
If conventional capacitor-based DRAM storage is used, then storage function is achieved, but device height increases reducing density
Solution Approach 1:
The patent extracts the storage function from the traditional capacitor structure and integrates it directly into the transistor gate structure. The gate of each transistor serves dual purposes as both control element and storage node, eliminating the need for separate tall capacitor structures and reducing overall device height while increasing storage density.
Solution Approach 2:
The transistor gate structure is designed to perform multiple functions: it acts as the control gate for transistor operation and simultaneously serves as the storage node for data retention. This multi-functional design eliminates redundant structures, reduces device height, and increases storage density in the vertically stacked architecture.
Data Source
AI summary
Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a semiconductor device includes a first transistor comprising a first channel region. The first channel region includes one or more first nanostructures formed of a semiconductor material. The semiconductor device includes a second transistor disposed vertically with respect to the first transistor and comprising a second channel region. The second channel region includes one or more second nanostructures formed of a conductive oxide material.