3D Hybrid Memory With Horizontal Channels for Dense DRAM Stacking
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Solution Overview
Problem
Current semiconductor manufacturing faces challenges in scaling transistors to single-digit nanometer nodes, with 2D circuits reaching density limits, and there is a need for 3D integration to increase transistor density in volume rather than area, particularly for logic chips like CPUs and GPUs, where 3D NAND implementation is more feasible than for random logic designs.
Innovation Solution
The development of non-planar, 3D semiconductor structures with conductive dielectric channels and Gate All Around (GAA) transistors, utilizing materials like indium oxide, tin oxide, and ferroelectric materials to create denser and thinner DRAM memory arrays by stacking transistors vertically and using high-k dielectric materials to enhance performance and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If 2D circuits are used to increase transistor density per unit area, then area efficiency is improved, but volume utilization deteriorates
Solution Approach 1:
The patent transitions from 2D planar circuits to 3D vertical stacking by introducing multiple transistor layers stacked vertically. Each transistor layer is formed at different heights above the substrate, utilizing the third dimension (vertical space) to increase overall transistor density while maintaining area efficiency. This dimensional transition resolves the contradiction by simultaneously improving both area utilization and volume utilization.
2Reliability
If conventional capacitors are used in DRAM memory arrays, then storage function is achieved, but device height increases reducing density
Solution Approach 1:
The patent merges the storage transistor and capacitor into an integrated structure where the storage transistor replaces the conventional separate capacitor component. The drain region of the access transistor serves dual functions as both the storage node and part of the transistor structure, eliminating the need for a separate tall capacitor and thereby reducing overall device height while maintaining storage functionality.
Solution Approach 2:
The access transistor's drain region is designed to serve multiple functions simultaneously: it acts as the storage node for data retention, the control electrode for charge storage, and an integral part of the transistor switching mechanism. This multi-functionality eliminates the need for separate dedicated capacitor structures, reducing device height while preserving storage function.
3Volume of moving object
If 3D vertical stacking is implemented to increase transistor density, then volume utilization is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the 3D structure into discrete transistor layers, each comprising channel regions, gate electrodes, and source/drain regions formed at specific height levels. This segmentation into standardized repeating units simplifies manufacturing by allowing modular fabrication processes to be applied repeatedly at different vertical levels, reducing overall manufacturing complexity despite the 3D architecture.
Solution Approach 2:
The patent employs preliminary patterning and positioning of channel regions and gate electrodes before final assembly and interconnection steps. By pre-forming channel regions with specific orientations and positions, and pre-positioning gate electrodes, the manufacturing process is simplified as subsequent steps build upon these pre-prepared structures rather than requiring complex simultaneous operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a higher 3D density of DRAM memory arrays, providing cost, performance, and design advantages by replacing conventional capacitors with more efficient storage transistors, enabling improved area efficiency and reliable storage/read operations.
Implementation Method 1
The gate structure comprises: (i) a first metal material, (ii) a ferroelectric material, and (iii) a second metal material
Implementation Method 2
utilizing materials like indium oxide, tin oxide, and ferroelectric materials to create denser and thinner DRAM memory arrays by stacking transistors vertically and using high-k dielectric materials to enhance performance and density
Implementation Method 3
The channel regions of the transistors may be oriented to conduct current through the channel in a direction generally parallel with the major surface of the system or chip upon which, or within which, these structures are provided
Data Source
AI summary
A semiconductor structure includes one or more first nanostructures extending along a first lateral direction; one or more second nanostructures extending along the first lateral direction and vertically disposed above the one or more first nanostructures; and a gate structure extending along a second lateral direction perpendicular to the first lateral direction, and disposed around each of the one or more first nanostructures and each of the one or more second nanostructures. The gate structure comprises: (i) a first metal material, (ii) a ferroelectric material, and (iii) a second metal material.