3D Integrated Circuit Stacking with Annealed 2D Semiconductor Seeds
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing integration density due to physical constraints in two-dimensional (2D) IC formation, particularly in reducing the minimum feature size of components.
Innovation Solution
The approach involves forming semiconductor islands on an amorphous surface of an interconnect structure, which allows for the creation of three-dimensional (3D) ICs by placing lower transistors at a lower level and higher transistors at a higher level. This is achieved by annealing defective 2D semiconductor seeds to form substantially defect-free seeds, which are then laterally grown into 2D semiconductor islands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional (2D) IC formation is used with repeated reductions in minimum feature size, then integration density improves, but physical constraints and manufacturing complexity increase
Solution Approach 1:
The patent transitions from two-dimensional (2D) integrated circuit formation to three-dimensional (3D) integrated circuit formation by stacking multiple transistor layers vertically. This dimensional change allows continued increase in integration density without further reducing minimum feature size, thereby avoiding the physical constraints and manufacturing complexity associated with continued 2D scaling.
2Quantity of substance
If minimum feature size is reduced to increase component integration, then more components fit in given area, but manufacturing precision requirements increase
Solution Approach 1:
By moving to 3D IC formation with vertically stacked transistor layers, the patent achieves higher component integration without requiring further reduction in minimum feature size. This maintains manageable manufacturing precision requirements while still increasing the number of components that can be integrated in a given area.
Solution Approach 2:
The patent changes the structural parameters of the integrated circuit from planar 2D layout to vertical 3D stacking. This parameter change allows integration density to increase through vertical space utilization rather than through continued reduction of lateral feature dimensions, thereby maintaining manufacturing precision within feasible limits.
3Ease of manufacture
If defective 2D semiconductor seeds are used directly, then manufacturing process is simpler, but crystalline defects reduce transistor quality
Solution Approach 1:
The patent performs preliminary annealing treatment on defective 2D semiconductor seeds before using them to form transistor channels. This preliminary action repairs crystalline defects in the seeds, thereby improving transistor quality without significantly complicating the manufacturing process.
Solution Approach 2:
The patent introduces an intermediate annealing process between seed formation and transistor fabrication. This intermediary step acts as a mediator that repairs crystalline defects in the semiconductor seeds, thereby improving the quality of subsequent transistor structures without requiring complete redesign of the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of 3D ICs with increased transistor density in a given area, overcoming the physical limits of 2D ICs by reducing crystalline defects and improving the quality of 2D semiconductor islands.
Implementation Method 1
annealing defective 2D semiconductor seeds to form substantially defect-free seeds
Implementation Method 2
laterally grown into 2D semiconductor islands
Data Source
AI summary
A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.