3D IC Bonding via Copper-Titanium Co-Deposition
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Solution Overview
Problem
Current bonding methods for three-dimensional integrated circuits are complex, limit manufacturing flexibility, and are not suitable for front-end processes, restricting the miniaturization and integration of functional chips.
Innovation Solution
A bonding method involving sequential deposition of metal co-deposition layers on substrates, followed by patterning and superimposition at a controlled temperature to form adhesive, barrier, and boundary protection layers, specifically using copper and titanium under atmospheric conditions to simplify the process and enhance adhesion and oxidation resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding methods using conductive copper pillars are used, then connection between integrated circuit chip and substrate is achieved, but the manufacturing process becomes complicated and difficult to manufacture
Solution Approach 1:
The patent combines multiple functions (adhesion, barrier, and protection layers) into a single co-deposition layer formed by depositing copper and titanium simultaneously. This eliminates the need for separate layers and simplifies the manufacturing process while maintaining connection reliability between the integrated circuit chip and substrate.
Solution Approach 2:
The co-deposition layer serves multiple functions simultaneously: it provides adhesion between the chip and substrate, acts as a diffusion barrier to prevent copper oxidation, and forms a protective boundary layer. This multi-functionality reduces the number of manufacturing steps required compared to conventional methods.
2Reliability
If conventional bonding methods are used, then integrated circuits can be connected, but the manufacturing process takes too much time and cannot be applied in front-end process
Solution Approach 1:
The adhesion and barrier layers are formed simultaneously with the metal interconnect structure during the co-deposition process, before subsequent manufacturing steps. This preliminary formation of protective layers eliminates the need for separate post-processing steps and reduces overall manufacturing time while ensuring bonding reliability.
Solution Approach 2:
Multiple manufacturing operations (deposition of adhesion layer, barrier layer, and protection layer) are merged into a single co-deposition step, significantly reducing the time required for front-end process integration while maintaining bonding reliability.
3Ease of manufacture
If copper is used without additional barrier layers, then manufacturing process is simplified, but copper atoms diffuse into film layers causing oxidation
Solution Approach 1:
The patent creates a composite co-deposition layer containing both copper and titanium atoms distributed throughout the structure. The titanium atoms form a barrier function within the composite material itself, preventing copper diffusion and oxidation while maintaining manufacturing simplicity through a single deposition process.
Solution Approach 2:
The co-deposition layer is self-protective, as the titanium atoms within the layer automatically form a barrier function that prevents copper oxidation without requiring external barrier layers. The structure serves its own protection needs, eliminating additional manufacturing steps.
4Manufacturing precision
If traditional manufacturing methods are used, then process control is maintained, but the degree of freedom in chip integration is limited
Solution Approach 1:
The patent changes the deposition parameters by using co-deposition with controlled atomic ratios of copper and titanium. This allows precise control over the composition and properties of the co-deposition layer, enabling adaptation to different integration requirements while maintaining manufacturing precision through controlled deposition conditions.
Solution Approach 2:
The co-deposition layer provides universal applicability for different integration scenarios, as it simultaneously delivers adhesion, barrier, and protection functions that can be adapted to various chip integration configurations without requiring different manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process, extends the degree of freedom in chip integration, and forms stable adhesion and barrier layers to prevent copper oxidation, enabling more efficient and flexible three-dimensional integrated circuit assembly.
Implementation Method 1
at least a portion of atoms of the first metal diffuse toward a bonding interface between the co-deposition layers and at least a portion of atoms of the second metal diffuse toward the respective film layers
Implementation Method 2
at least another portion of the atoms of the second metal at peripheries of the co-deposition layers react with oxygen, and thereby forming a boundary protection layer to protect the first metal from oxidization
Implementation Method 3
the co-deposition layers thereof are bonded with each other, and at least a portion of atoms of the first metal diffuse toward a bonding interface
Data Source
AI summary
The present invention discloses a bonding method for a three-dimensional integrated circuit and the three-dimensional integrated circuit thereof. The bonding method comprises the steps of: providing a substrate; depositing a film layer on the substrate; providing a light source to light onto the film layer to form a graphic structure; forming a metal co-deposition layer by a first metal and a second metal that are co-deposited on the film layer; providing a first integrated circuit having the substrate, the film layer and the metal co-deposition layer sequentially; providing a second integrated circuit that having the metal co-deposition layer, the film layer and the substrate sequentially; and the first integrated circuit is bonded with the second integrated circuit at a predetermined temperature to form a three-dimensional integrated circuit.