3D IC Circuit Cell Partitioning via Dynamic Frames
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Solution Overview
Problem
Current 3D IC manufacturing processes face challenges in efficiently partitioning and routing circuit cells across stacked tiers, leading to increased wire lengths and uneven distribution, which affects the routing quality and efficiency of three-dimensional integrated circuits.
Innovation Solution
A method involving a processor and memory system that shrinks circuit cell sizes, partitions them into dynamic frames across multiple tiers, and adjusts cell distributions based on balance factors and step sizes to minimize connections and wire lengths, using a dynamic frame size approach for improved distribution and routing quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If circuit cells are partitioned using fixed frame size methods, then the partitioning process is simple, but the distribution of circuit cells across tiers becomes uneven and wire lengths increase
Solution Approach 1:
The patent applies dynamics by transitioning from fixed frame size to dynamic frame size that adapts during the partitioning process. The frame size changes based on the distribution state of circuit cells, allowing the system to optimize placement quality automatically as partitioning progresses, thereby achieving both operational feasibility and manufacturing precision.
Solution Approach 2:
The patent changes the parameter of frame size from static to dynamic. By adjusting the frame size parameter during the partitioning process based on real-time distribution feedback, the system achieves improved circuit cell distribution uniformity across tiers while maintaining process simplicity through automated parameter adaptation.
2Manufacturing precision
If dynamic frame size is used to improve circuit cell distribution, then routing quality improves, but the complexity of the partitioning algorithm increases
Solution Approach 1:
The patent applies self-service by designing an algorithm that automatically adjusts frame size based on its own execution state and distribution feedback. The system serves itself by making autonomous decisions about parameter adjustments without external intervention, improving routing quality while containing complexity through self-regulation mechanisms.
Solution Approach 2:
The patent implements feedback by continuously monitoring circuit cell distribution across tiers and using this information to adjust the frame size parameter. This closed-loop control mechanism improves routing quality by adapting to actual distribution states, while managing algorithmic complexity through systematic feedback processing rather than exhaustive search methods.
3Area of stationary object
If circuit cells are densely packed to improve integration, then area utilization increases, but wire connections become longer and routing becomes more difficult
Solution Approach 1:
The patent addresses the wire length issue by considering three-dimensional tier assignments rather than purely two-dimensional placement. By dynamically adjusting frame sizes and making strategic decisions about which cells to place in which tiers, the system optimizes both area utilization and wire length by exploiting the vertical dimension of 3D IC architecture.
Data Source
AI summary
A method includes following operations. First circuit cells are partitioned into a first frame of a first tier and the first frame of a second tier. The first frame is divided into second frames according to a step size. The first circuit cells between the second frames of the first tier and the second tier are adjusted. The first tier and the second tier, to which the adjusted first circuit cells are assigned, are merged to generate data indicating a layout design, for fabrication of the circuit cells.