3D IC Clock Tree Synthesis for Low Cost Pre-Bond Testing

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Solution Overview

Problem

Pre-bond testing of 3D integrated circuits faces challenges due to the need for complete 2D clock trees across multiple tiers, leading to long wirelength and high clock power consumption, as well as complex testing requirements with multiple probe pads, which increase design-for-testing costs.

Innovation Solution

A fully connected 2D clock tree on a backbone die and multiple isolated 2D clock trees on non-backbone dies, connected using a Detachable tree (D-tree) with multiple through-silicon-vias, allowing for pre-bond testing with a single clock probe pad and subsequent removal of the D-tree for post-bond operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a complete 2D clock tree is built on each individual die with a single TSV connection, then pre-bond testing can be enabled, but wirelength increases and clock power consumption increases due to additional buffers

Engineering Contradiction:
Improvepre-bond testabilityVSAvoidclock power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The clock tree on non-backbone dies is segmented into multiple isolated 2D clock trees that are disconnected after pre-bond testing. During pre-bond testing, these segmented trees are connected via D-tree to enable single-probe testing. After testing, the connections are severed, eliminating the need for buffers and reducing clock power consumption in the final product.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The D-tree connections and transmission gates are preliminarily configured to enable pre-bond testing before the actual bonding process. The transmission gates are initially enabled to connect the segmented clock trees, allowing test access. After pre-bond testing completes successfully, the transmission gates are disabled to remove the D-tree from the clock distribution network, optimizing post-bond performance.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If multiple TSVs and an R-tree are used to connect non-backbone dies, then a single clock probe pad can be used for pre-bond testing, but DFT cost increases due to transmission gates requiring global connections

Engineering Contradiction:
Improvetest probe complexityVSAvoidDFT cost
Core Design Contradiction:
Device complexityVSEase of manufacture

Solution Approach 1:

The clock tree is segmented into multiple isolated 2D clock trees on non-backbone dies, connected during pre-bond testing via a segmented D-tree structure using multiple TSVs. After pre-bond testing, these segments are disconnected, eliminating the need for expensive transmission gates and global control connections required by traditional R-tree approaches.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The D-tree connection structure is extracted and removed from the clock distribution network after pre-bond testing by disabling transmission gates and burning fuses. This extraction eliminates the DFT overhead of maintaining permanent R-tree connections with transmission gates, reducing DFT cost while preserving the benefit of single-probe pre-bond testing capability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Device complexity

If a single TSV connects 2D clock trees on adjacent dies, then the structure is simple, but wirelength increases and more buffers are needed

Engineering Contradiction:
Improveclock tree structureVSAvoidwirelength
Core Design Contradiction:
Device complexityVSLength of stationary object

Solution Approach 1:

The solution transitions from a 2D single-TSV connection approach to a 3D multi-TSV architecture. Multiple TSVs are used to connect corresponding clock trees across adjacent dies in the vertical dimension, reducing the wirelength on each die and eliminating the need for extensive buffer chains while maintaining structural simplicity through standardized vertical interconnects.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9508615B2Clock tree synthesis for low cost pre-bond testing of 3D integrated circuits
Publication Date: 2016.11.29 QUALCOMM INC
  • US9508615B2 patent drawing
  • US9508615B2 patent drawing
  • US9508615B2 patent drawing

AI summary

To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees.