3D IC Crack Stop Circumferential Wall
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Solution Overview
Problem
3D integrated circuits face challenges in preventing crack propagation during dicing and thermal expansion, as existing techniques lack effective methods to include crack stop structures across bonded interfaces, particularly in thinned substrate layers, leading to potential circuit failure.
Innovation Solution
A circumferential wall is formed through the bonding layer and adjacent to the periphery of the 3D IC structure, using a tough material, which can be the same as the TSV, to prevent crack propagation, and this wall can be created before or after bonding the components together, simultaneously with forming TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a narrow crack stop region is formed around the periphery of a 2D integrated circuit chip, then crack propagation is blocked, but the chip area available for active circuitry is reduced
Solution Approach 1:
The patent transitions from 2D planar crack stops to 3D vertical circumferential walls that extend through the substrate thickness. This dimensional change allows the crack stop function to be achieved without consuming lateral chip area, as the protection is provided in the vertical dimension rather than the horizontal plane.
Solution Approach 2:
The circumferential wall is formed only in the peripheral region of the chip where crack initiation is most likely, rather than throughout the entire chip. This localized approach provides crack protection where needed while preserving maximum chip area for active circuits.
2Adaptability or versatility
If the substrate is thinned to enable TSV formation for 3D integration, then 3D IC capabilities are achieved, but the substrate becomes more susceptible to dicing damage and crack propagation
Solution Approach 1:
The circumferential wall is formed in the thinned substrate before dicing occurs. This preliminary structural reinforcement prevents dicing damage from propagating into the active area, addressing the vulnerability created by substrate thinning needed for TSV formation.
Solution Approach 2:
The circumferential wall acts as a protective barrier that absorbs and deflects dicing forces before they can reach the active circuit region. This beforehand cushioning effect protects the thinned substrate from damage during the subsequent dicing process.
3Productivity
If wafer-scale bonding is used to form 3D ICs, then manufacturing throughput is increased, but dicing flaws can propagate into the active area causing circuit failure
Solution Approach 1:
The circumferential wall segments the chip into a protected active interior region and a peripheral region that can safely contain dicing flaws. This segmentation allows wafer-scale processing while preventing flaw propagation into the active area during subsequent dicing.
Solution Approach 2:
The circumferential wall serves as an intermediary barrier between the dicing process and the active circuit region. It intercepts and contains dicing-induced flaws, preventing them from reaching and damaging the active circuits while allowing high-volume wafer processing.
Data Source
AI summary
The present invention relates to bonded semiconductor integrated circuits, more specifically to a structure to protect against crack propagation into any layer of such integrated circuits. Embodiments of the present invention may include a first semiconductor substrate having a first layer bonded to second layer of a substantially thinner second semiconductor substrate by a bonding layer. The first layer may contain a crack stop. The crack stop may be in contact with a circumferential wall, made up of posts, that extends through the bonding layer, the second layer, and the second substrate.