3D IC Stabilization via Inter-Chip Decoupling Capacitors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional integrated circuits face challenges in stabilizing power supply voltage due to voltage drops, particularly in high-current semiconductor chips, as existing methods require additional processes and materials that increase cost and parasitic capacitance, affecting signal delay and yield.
Innovation Solution
The integration of a second ground wiring layer or second power supply wiring layer between semiconductor chips in a three-dimensional integrated circuit, formed using ordinary fabrication steps, to create decoupling capacitors that stabilize power supply voltage without additional process steps or materials, allowing concurrent rewiring and increased capacitor capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a film capacitor is interposed between semiconductor chips to stabilize power supply voltage, then the power supply stability is improved, but the manufacturing cost increases due to additional materials and process steps
Solution Approach 1:
The patent merges the decoupling capacitor function with the existing power supply and ground wiring layers of the semiconductor chips. Instead of adding separate film capacitors, the capacitor is formed by utilizing the capacitance between adjacent power supply and ground wiring layers that are already present in the chip structure, thereby eliminating additional materials and process steps while maintaining power supply stability
Solution Approach 2:
The power supply and ground wiring layers serve dual functions: their primary function is to supply power and ground connections to the circuit, and their secondary function is to form a decoupling capacitor between adjacent chips. This multi-functionality eliminates the need for dedicated capacitor structures, reducing manufacturing complexity and cost
2Reliability
If a film capacitor is interposed between semiconductor chips to stabilize power supply voltage, then the power supply stability is improved, but the manufacturing complexity increases due to additional process steps
Solution Approach 1:
The patent combines the capacitor formation process with the existing wiring layer fabrication process. The same photolithography and metallization steps used to create power supply and ground wiring layers are also used to form the capacitor electrodes, thereby integrating capacitor manufacturing into the standard chip fabrication flow without adding separate process steps
3Reliability
If additional contacts are added between chips and film capacitor to improve power supply stability, then the power supply stability is improved, but the manufacturing yield deteriorates
Solution Approach 1:
The patent merges the capacitor contacts with the existing TSV (Through-Silicon Via) structures used for chip-to-chip connections. The same vias that connect circuit elements between chips are also used to connect to the capacitor electrodes, thereby utilizing existing contact structures for dual purposes and avoiding additional contacts that would reduce yield
4Reliability
If high dielectric film is used between semiconductor chips to form high capacity capacitor, then the capacitor capacity is increased, but the signal line parasitic capacitance increases causing greater signal delay
Solution Approach 1:
The patent applies local quality by positioning the high-capacitance structure only where needed for power supply stabilization. The capacitor is formed locally between adjacent power supply and ground wiring layers at specific locations on the chip surface, rather than using a uniform high dielectric film across the entire chip, thereby providing high capacitor capacity at the power supply nodes while minimizing parasitic capacitance on signal lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively stabilizes power supply voltage by forming high-capacity decoupling capacitors near semiconductor chips, reducing costs and improving yield while minimizing signal delay, as the additional wiring layers enhance power supply stability without requiring specific process steps or materials.
Implementation Method 1
the arrangement of the high dielectric film increases a parasitic capacitance of the signal line between the semiconductor chips
Data Source
AI summary
The three-dimensional integrated circuit has a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein each of the first semiconductor chip and the second semiconductor chip is provided with a power supply wiring layer which has a wiring pattern structure for stably supplying a power supply voltage to an internal circuit of the semiconductor chip, and a ground wiring layer in succession, and one of the first semiconductor chip and the second semiconductor chip further includes a second ground wiring layer or a second power supply wiring layer on a surface facing to the other semiconductor chip.