3D Single-Crystal IC Stacking for Dense Interlayer Connections
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and existing 3D IC technologies are constrained by large Through-Silicon Vias (TSVs) that restrict the number of connections that can be made.
Innovation Solution
The development of a 3D IC device fabrication method using a programmable antifuse structure with Through-Silicon Via (TSV) technology, allowing for the construction of configurable logic devices with multiple layers of antifuses for power distribution and interconnection, and employing layer transfer techniques to create thin, high-density connections, reducing the size and increasing the density of interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent applies antifuse structures that can be programmed after fabrication to dynamically configure logic functions. The antifuse elements can be selectively broken to create or disconnect conductive paths, enabling reconfigurable logic families without requiring new mask sets for each product configuration.
Solution Approach 2:
The invention changes the electrical state of antifuse elements by applying voltage to break the insulating layer and create conductive paths. This parameter change (from insulating to conducting state) enables post-fabrication programming and reconfiguration of logic functions, providing flexibility without additional mask sets.
2Productivity
If Through-Silicon Via (TSV) technology is used for 3D IC connections, then interconnection is enabled, but the size of TSVs is large which restricts the number of connections
Solution Approach 1:
The patent segments the interconnection function into multiple smaller components: through-silicon vias for vertical connections, antifuse elements for logic configuration, and interlayer vias for horizontal connections. This segmentation allows optimized sizing of each element type, enabling higher connection density without requiring large TSV dimensions.
Solution Approach 2:
The invention adds vertical dimension to the interconnection architecture by stacking multiple layers with through-silicon vias and interlayer vias. This three-dimensional interconnection approach increases the number of possible connections without increasing the lateral footprint or individual via size, effectively bypassing the limitation imposed by large TSV dimensions.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a first oxide layer disposed atop of the first level; a second level including second transistors and at least one array of memory cells, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where the at least one of the second transistors includes a recessed channel, and where the second level is directly bonded to the first level.