3D IC Design Partitioning for TSV Reduction
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Solution Overview
Problem
Current CAD tools face challenges in optimizing the design of monolithic three-dimensional integrated circuits, particularly in minimizing the number of Through-Silicon Vias (TSVs) and leveraging dense inter-layer connectivity to enhance object placement and proximity in 3D space, which is not effectively addressed by traditional 2D CAD tools.
Innovation Solution
The solution involves extending CAD tool functionality to perform partitioning and placement across multiple strata using 2D placers and routers, optimizing for disparate characteristics of each layer, such as lithography requirements, power dissipation, and manufacturing costs, while utilizing existing 2D CAD tools for 3D IC design by partitioning logic and memory layers and assigning appropriate placement based on these criteria.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional 2D CAD tools are used for 3D IC design, then the existing tool functionality is maintained, but the ability to optimize for dense inter-layer connectivity and minimize TSVs is insufficient
Solution Approach 1:
The patent extends traditional 2D CAD tool functionality to handle 3D IC design by introducing vertical dimension operations. The system partitions 3D IC designs into multiple strata (front, middle, back) and performs placement and routing operations that consider three-dimensional spatial relationships, thereby enabling optimization for dense inter-layer connectivity while minimizing through-silicon via (TSV) requirements.
2Productivity
If partitioning and placement across multiple strata is performed, then inter-layer connectivity is optimized, but the complexity of the design process increases
Solution Approach 1:
The patent divides the 3D IC design process into distinct phases: partitioning the design into multiple strata, performing placement operations on each stratum separately, and then executing routing across the partitioned structure. This segmentation allows the complex 3D optimization problem to be broken down into manageable sub-problems that can be solved sequentially using extended 2D CAD tool capabilities.
Data Source
AI summary
A method of designing a 3D Integrated Circuit, the method including: partitioning at least one design into at least two levels, a first level and a second level; providing connections placement data of the second level, where the connections include planned connections between the first level and the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the connections placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; and performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.