3D IC Device Partitioning for Area Loading Balance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D IC fabrication techniques face challenges in optimizing the integration density and complexity of semiconductor components, particularly due to noise sources from TSV-to-TSV coupling and the complexity of inter-tier connections in stacked tiers, which limits the efficient use of horizontal space on PCBs.
Innovation Solution
A method involving the selection and substitution of devices with matching electrical characteristics for assignment to specific tiers in a 3D IC, where p-MOSFETs and n-MOSFETs are assigned to different tiers based on symmetry and area loading, allowing for efficient partitioning and area minimization through sequential assignment and geometry matching recognition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If through substrate vias (TSV) are used in 3D IC packages, then vertical stacking and area savings are achieved, but fabrication complexity and noise coupling increase
Solution Approach 1:
The patent extracts the problematic TSV-to-TSV coupling noise source by separating p-MOSFETs and n-MOSFETs into different tiers, eliminating the harmful electromagnetic coupling between adjacent TSVs that carry complementary signals
Solution Approach 2:
The patent segments the circuit network by dividing devices into different tiers based on their type (p-MOSFET vs n-MOSFET), creating spatial separation that reduces noise coupling while maintaining functional integration
2Quantity of substance
If devices are assigned to multiple tiers in 3D IC, then integration density improves, but inter-tier connection complexity increases
Solution Approach 1:
The patent applies local quality by assigning specific device types (p-MOSFETs or n-MOSFETs) to specific tiers based on their electrical characteristics and noise coupling considerations, optimizing both density and managing complexity through localized assignment rules
3Area of stationary object
If device area is minimized in 3D IC tiers, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the parameter of device assignment by using total area loading as the optimization criterion, balancing area distribution across tiers through systematic assignment algorithms that consider both device size and tier capacity
Data Source
AI summary
A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from largest device area to smallest device area; and assigning each second device in the selected network to be fabricated in a respective one of a plurality of tiers of a 3D IC for which a total area of second devices previously assigned to that tier is smallest, the second devices being assigned sequentially according to the sorting.