3D Wide-Bandgap IC Die Stacking for Low-Inductance Switching
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Solution Overview
Problem
Existing semiconductor devices based on gallium nitride (GaN) face challenges with back-gating effects and high parasitic inductance due to the common substrate acting as a back gate, leading to reduced switching performance and increased area occupation.
Innovation Solution
A three-dimensional (3D) semiconductor structure is implemented, where high-side and low-side transistors are split across two IC dies, vertically stacked and bonded through a bond structure, eliminating wire bonding and reducing parasitic inductance, while using separate substrates to mitigate back-gating effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If high-side and low-side transistors are integrated on a common substrate, then device area is reduced, but back-gating effects and parasitic inductance increase
Solution Approach 1:
The patent divides the integrated circuit into two separate IC dies: a first IC die containing the high-side transistor and a second IC die containing the low-side transistor. This segmentation eliminates the back-gating effect by isolating the transistors on different substrates and reduces parasitic inductance by enabling direct bonding between dies, thereby maintaining compact form factor while improving switching performance.
2Reliability
If transistors are separated onto different IC dies, then back-gating effects are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent combines two separately manufactured IC dies (first IC die with high-side transistor, second IC die with low-side transistor) through direct bonding to create a unified integrated circuit assembly. This merging approach maintains the benefits of separate substrates for eliminating back-gating effects while achieving integration that simplifies the overall manufacturing process compared to traditional wire bonding or hybrid assembly methods.
3Reliability
If traditional wire bonding is used to connect transistors, then electrical coupling is achieved, but parasitic inductance increases
Solution Approach 1:
The patent extracts and eliminates the wire bonding interconnection layer by directly bonding the first IC die to the second IC die. This removal of the intermediate wire bonding step significantly reduces parasitic inductance in the electrical coupling path between the high-side and low-side transistors, thereby improving switching performance while simplifying the interconnection structure.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a three-dimensional (3D) semiconductor structure for wide-bandgap semiconductor devices in which the wide-bandgap semiconductor devices are split amongst a first IC die and a second IC die. The first IC die includes a first substrate and a first semiconductor device. The first substrate includes a first wide-bandgap material, and the first semiconductor device overlies the first substrate and is formed in part by the first wide-bandgap material. The second IC die overlies the first IC die and is bonded to the first IC die by a bond structure between the first and second IC dies. Further, the second IC die includes a second substrate and a second semiconductor device. The second substrate includes a second wide-bandgap material, and the second semiconductor device underlies the second substrate and is formed in part by the second wide-bandgap material.