3D IC Floorplanning via Simulated Annealing
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Solution Overview
Problem
Current 3D IC design techniques lack effective methods for optimizing floorplanning across multiple layers, failing to consider manufacturability and design constraints, which leads to inadequate global optimization and increased thermal issues due to higher power density and poor thermal conductivity.
Innovation Solution
A system using simulated annealing to iteratively perturb and optimize the arrangement of circuit blocks across layers, considering parameters like area, wirelength, TSVs, and thermal constraints, with a cost function that balances these factors, and incorporating slack-based movements to enhance block placement and wirelength optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If 3D IC technology is used to increase integration density and reduce system size, then area utilization improves, but thermal management becomes more difficult due to higher power density and poor thermal conductivity of dielectric layers
Solution Approach 1:
The patent transitions from 2D planar floorplanning to 3D floorplanning by adding the z-dimension (layer stacking) to the design space. This allows circuit blocks to be distributed across multiple layers, increasing integration density and reducing system footprint while providing new degrees of freedom for thermal management through vertical heat dissipation paths and strategic block placement.
Solution Approach 2:
The patent applies local quality by allowing different regions and layers of the 3D IC to have different thermal characteristics and block densities. The floorplanning algorithm can place heat-generating blocks in regions with better thermal conductivity or closer to heat sinks, while positioning sensitive blocks in cooler regions, thereby addressing thermal management locally throughout the structure.
2Device complexity
If conventional 2D floorplanning techniques are extended to 3D ICs, then implementation simplicity is maintained, but global optimization is insufficient and manufacturability constraints are not considered
Solution Approach 1:
The patent segments the floorplanning problem into multiple independent cost components (area cost, wirelength cost, TSV cost, aspect ratio cost, thermal cost) that can be evaluated and optimized separately. This segmentation allows the complex 3D floorplanning problem to be broken down into manageable parts while still achieving global optimization through the comprehensive cost function.
Solution Approach 2:
The patent creates a universal floorplanning framework that simultaneously optimizes multiple objectives (area, wirelength, TSV count, aspect ratio, thermal performance) and incorporates various manufacturing constraints. This multi-functional cost function serves as a comprehensive evaluation metric that guides the optimization toward solutions that satisfy both performance and manufacturability requirements.
3Area of stationary object
If circuit blocks are densely packed to maximize area utilization, then area efficiency improves, but wirelength and thermal issues worsen
Solution Approach 1:
The patent utilizes the z-dimension to reduce wirelength by allowing connections to traverse vertically between layers through TSVs. This three-dimensional routing capability enables shorter interconnect paths compared to 2D planar routing, as blocks can be placed closer to their connection points in the vertical dimension, thereby reducing overall wirelength while maintaining high area efficiency.
Solution Approach 2:
The patent merges multiple optimization objectives (area efficiency, wirelength minimization, thermal management) into a single unified cost function. This combination allows the floorplanning algorithm to find balanced solutions that achieve high area efficiency without excessively increasing wirelength or thermal problems, as the cost function penalizes extreme configurations across all dimensions simultaneously.
Data Source
AI summary
One embodiment of the present invention provides a system for facilitating floorplanning for three-dimensional integrated circuits (3D ICs). During operation, the system receives a number of circuit blocks. The system places the blocks in at least one layer of a multi-layer die structure and sets an initial value of a time-varying parameter. The system then iteratively perturbs the block arrangement until the time-varying parameter reaches a pre-determined value.