3D IC Assembly with Intermediary Die for Hybrid Bond Alignment
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Solution Overview
Problem
Conventional 3D wafer packaging methods, such as hybrid bonding, require precise alignment and rearrangement of devices and circuitry, leading to inefficiencies in processing and manufacturing.
Innovation Solution
The proposed solution involves an integrated circuit assembly with a third bare die positioned between two semiconductor dies, where hybrid bonding is used to align bonding points between the insulation layers, and through vias and internal routing layers facilitate electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hybrid bonding is used to align bonding points between dies, then bonding reliability is improved, but device rearrangement complexity increases
Solution Approach 1:
The patent divides the bonding process into two separate operations: first bonding the third bare die to the first bare die, then bonding the fourth insulation layer to the second bare die. This segmentation eliminates the need for complex device rearrangement while maintaining bonding reliability, as each bonding operation can be performed independently with standard alignment procedures.
Solution Approach 2:
The third bare die acts as an intermediary component between the first and second bare dies. By introducing this intermediate layer with through vias and routing layers, the patent enables electrical connection between devices on different dies without requiring precise alignment of bonding points, thus reducing rearrangement complexity while maintaining reliable bonding.
2Manufacturing precision
If device rearrangement is performed for alignment, then bonding precision is improved, but processing efficiency decreases
Solution Approach 1:
The patent performs preliminary routing and via formation on the third bare die before the bonding process. The routing layers and through vias are pre-configured to establish electrical connections, so that when bonding occurs, no additional rearrangement or routing adjustments are needed, thereby maintaining both precision and efficiency.
Solution Approach 2:
The patent transitions from planar routing to three-dimensional routing by utilizing vertical through vias in the third bare die. This dimensional change allows electrical connections to be established through the thickness of the die rather than requiring complex lateral routing, simplifying the bonding process and improving processing efficiency while maintaining precision.
3Reliability
If through vias and routing layers are added for electrical connection, then connectivity is improved, but structure complexity increases
Solution Approach 1:
The third bare die serves multiple functions simultaneously: it provides mechanical support as a substrate, establishes electrical connections through through vias, and routes signals through routing layers. By consolidating these multiple functions into a single component, the patent improves electrical connectivity without proportionally increasing overall structure complexity.
Solution Approach 2:
The routing layers are nested within the third bare die structure, with conductive patterns embedded in the insulation layers. The through vias are nested within the die substrate, creating a compact three-dimensional arrangement that provides comprehensive electrical connectivity while minimizing the increase in external structural complexity.
Data Source
AI summary
An integrated circuit assembly includes a first die formed by a first wafer layer and a first insulation layer, a second die formed by a second wafer layer and a second insulation layer, a third die formed by a third wafer layer, a third insulation layer, and a fourth insulation layer. A first semiconductor device is formed in the first wafer layer and forms a first bonding point on the first insulation layer. A second semiconductor device is formed in the second wafer layer and forms a second bonding point on the second insulation layer. A third bonding point of the third insulation layer and a fourth bonding point of the fourth insulation layer are connected through the interior of the third wafer layer. The third insulation layer and the first insulation layer are hybrid bonded and the fourth insulation layer and the second insulation layer are hybrid bonded.