3D IC Device Layer Interconnects for Low-Capacitance Signal Routing
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Solution Overview
Problem
Conventional approaches to electrically coupling device layers in three-dimensional (3D) integrated circuits (ICs) result in significant area penalties and undesirable electrical performance due to excessive capacitive coupling, limiting signaling speed.
Innovation Solution
The implementation of dense and readily fabricated device layer interconnects that provide a conductive connection between frontside and backside interconnects in 3D ICs, using techniques such as forming device layer interconnects in diffusion or gate regions of a dummy transistor, and filling trenches with metal to reduce capacitance and enhance signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional approaches are used to electrically couple device layers in 3D ICs, then the structure is simple to implement, but the area increases significantly and capacitive coupling becomes excessive
Solution Approach 1:
The patent transitions from planar 2D interconnect routing to 3D vertical interconnect routing through the device layer. Device layer interconnects extend vertically through the substrate, enabling signals to traverse between frontside and backside device layers in the third dimension, thereby reducing the lateral area required for signal routing while maintaining electrical coupling functionality.
Solution Approach 2:
The device layer interconnects are formed by nesting conductive structures within the device layer substrate itself. The interconnects are embedded within the silicon or semiconductor material of the device layer, utilizing the substrate volume rather than occupying additional lateral space, thus reducing area penalty while providing electrical coupling.
2Ease of manufacture
If conventional approaches are used to electrically couple device layers in 3D ICs, then the implementation is straightforward, but capacitive coupling becomes excessive and signaling speed decreases
Solution Approach 1:
By routing interconnects vertically through the device layer in the third dimension, the patent reduces the lateral distance and overlapping area between signal lines, thereby minimizing capacitive coupling. This vertical routing approach maintains ease of implementation through standard semiconductor fabrication processes while significantly improving signaling speed by reducing capacitive effects.
3Productivity
If device layer interconnects are formed in diffusion or gate regions of dummy transistors, then high-density connections are achieved, but the device layer structure becomes more complex
Solution Approach 1:
The patent utilizes dummy transistor structures to serve dual purposes: maintaining device layer continuity and providing pathways for vertical interconnects. The diffusion regions and gate regions of dummy transistors are repurposed as conduits for device layer interconnects, enabling high-density connections without requiring separate dedicated interconnect structures, thus managing complexity while maximizing connection density.
Solution Approach 2:
The device layer structure serves its own interconnect function by utilizing its existing diffusion and gate regions. Rather than requiring external or additional interconnect structures, the device layer itself provides the vertical coupling pathways through its inherent structural elements, achieving high-density connections while minimizing added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These interconnects enable high-density, low-capacitance connections for efficient signal routing between the frontside and backside of 3D ICs, improving electrical performance and supporting modern computing applications.
Implementation Method 1
the device layer interconnect is in conductive contact with a first source/drain region at a first surface of the device layer interconnect and a second source/drain region at a second, opposite surface of the device layer interconnect
Data Source
AI summary
Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.