3D IC Interposer TSV Segmentation for Active Area Preservation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Two-dimensional integrated circuits face physical limitations in integration density and increased interconnections lead to circuit RC delay and power consumption issues, prompting the need for three-dimensional integrated circuits (3DICs) without through-silicon vias (TSVs) in active dies.
Innovation Solution
The formation of three-dimensional integrated circuits using interposers with through substrate vias (TSVs) and intermediate interposers, where active dies are bonded to interposers without TSVs, allowing for increased active areas and eliminating issues associated with TSVs in active dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If through-silicon vias (TSVs) are formed in active dies to create 3D ICs, then vertical interconnections are achieved, but active area is reduced and manufacturing complexity increases
Solution Approach 1:
The patent segments the 3D IC structure into distinct functional layers: active dies without TSVs are separated from interposer structures that contain the TSVs. This segmentation allows active dies to maintain full active area while interposers provide the vertical interconnection functionality through their own TSVs, resolving the contradiction between vertical interconnection needs and active area preservation.
Solution Approach 2:
The patent introduces interposers as intermediary structures between active dies. These interposers act as mediators that contain the TSVs and handle vertical interconnections, allowing active dies to remain free of TSVs and maintain full active area. The interposers translate and adapt the connection interfaces between different die layers, solving the contradiction by placing TSVs in the intermediary rather than in the active dies.
2Productivity
If more devices are integrated into one chip to increase integration density, then component count increases, but interconnection complexity and RC delay increase
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking multiple active dies on interposers. This dimensional change allows numerous devices to be integrated across multiple layers without increasing interconnection complexity on any single layer, as vertical TSVs in interposers provide direct through-connectors between layers, reducing the number of interconnections required compared to 2D scaling.
3Length of moving object
If through-silicon vias (TSVs) are formed in active dies, then vertical connections are established, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the TSV formation process to interposers only, separating it from active die fabrication. This segmentation allows TSVs to be formed in dedicated interposer structures that are optimized for TSV processing, while active dies can be manufactured with standard precision requirements. The interposers act as sacrificial or dedicated structures that absorb the manufacturing precision demands of TSV formation.
Solution Approach 2:
The interposers serve as intermediary structures that bear the manufacturing precision burden of TSV formation and alignment. By placing TSVs in interposers rather than active dies, the precision requirements are isolated to the interposer fabrication and bonding processes, while active die manufacturing maintains relaxed precision tolerances. The interposers mediate the alignment between upper and lower die layers through their TSV structures.
Data Source
AI summary
A three-dimensional integrated circuit is disclosed, including a first interposer including through substrate vias (TSV) therein and circuits thereon; a plurality of first active dies disposed on a first side of the first interposer, a plurality of first intermediate interposers, each including through substrate vias (TSV), disposed on the first side of the first interposer, and a second interposer including through substrate vias (TSV) therein and circuits thereon supported by the first intermediate interposers.