3D IC In-Field Lane Testing and Repair
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Solution Overview
Problem
Existing technologies are unable to efficiently screen and repair defects in 3D IC lane communications in-field, as they require multiple dies to be brought offline, which is not feasible for data centers and server SOCs.
Innovation Solution
The system and method for in-field lane testing and repair, which includes a built-in self-test (BIST) unit capable of performing lane tests and repairs while resources are in different clock domains, allowing for predictive lane substitution before failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple dies are brought offline for lane testing and repair, then testing and repair accuracy is improved, but system availability and productivity deteriorate
Solution Approach 1:
The patent segments the testing and repair process into independent lane-level operations that can be performed individually without shutting down the entire system. Each lane can be tested and repaired independently while other lanes continue to operate, allowing precision testing without system-wide downtime.
Solution Approach 2:
The patent implements predictive lane substitution where replacement lanes are prepared in advance and pre-configured. When a lane defect is detected, the system can immediately switch to the pre-prepared replacement lane without requiring offline testing or repair operations, thus maintaining system availability while ensuring testing accuracy through proactive rather than reactive approaches.
2Difficulty of detecting and measuring
If multiple dies are brought offline for lane testing, then defect detection capability is improved, but operational complexity increases
Solution Approach 1:
The patent implements built-in self-test (BIST) functionality within the lanes themselves, allowing each lane to autonomously detect its own defects without requiring external testing equipment or system shutdown. The lanes perform self-diagnosis and can trigger replacement automatically, reducing operational complexity while maintaining high defect detection capability.
Solution Approach 2:
The system incorporates continuous monitoring and feedback mechanisms that detect lane defects in real-time during normal operation. Performance information from sensors feeds back to the control system, which automatically initiates lane substitution when defects are detected, eliminating the need for complex offline testing procedures while maintaining accurate defect detection.
3Productivity
If traditional 3D IC stacking is used, then computational throughput is improved, but interconnect reliability deteriorates due to increased complexity
Solution Approach 1:
The patent implements redundant replacement lanes that are pre-configured and ready before defects occur. This predictive approach allows the system to maintain high computational throughput by having backup interconnects prepared in advance, preventing reliability issues from impacting performance when defects are detected through continuous monitoring.
Solution Approach 2:
The system dynamically changes operational parameters by switching between functional lanes and replacement lanes based on real-time performance monitoring. When a lane defect is detected, the system reconfigures the interconnect topology by redirecting traffic to alternative lanes, maintaining reliability while preserving the high throughput capabilities enabled by 3D stacking.
Data Source
AI summary
Techniques and mechanisms for an integrated circuit (IC) die to support in-field testing and/or repair of a lane in a three-dimensional (3D) IC which is formed with multiple IC dies. In an embodiment, the 3D IC comprises test units which each correspond to a different partition comprising respective circuit resources. During in-field operation of the 3D IC, a given test unit is operable to detect both a first condition wherein two partitions are each in an idle state, and a second condition wherein a first link between the two partitions fails to satisfy a performance criteria. The idle states are indicated by a power management controller (PMC) agent during runtime operation of the 3D IC. In another embodiment, one or more test units configure an operational mode, based on the detected conditions, to substitute communication via the first lane with communication via a repair lane.