3D IC Fabrication via Layer Transfer and TSV Reduction
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and limited flexibility, particularly in constructing commercially viable logic families with diverse products, and they struggle with reducing inter-chip interconnects, which dominate IC performance and power consumption.
Innovation Solution
The development of a method for fabricating 3D Integrated Circuit (IC) devices using a layered structure with Through-Silicon-Via (TSV) connections, incorporating antifuse layers for configurable logic and memory, and employing layer transfer techniques to reduce the size and number of TSVs, enabling more efficient interconnects and cost-effective manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is limited
Solution Approach 1:
The patent segments the fabrication process into multiple stages using layer transfer technology. Different logic family layers can be fabricated separately and then transferred to a common substrate, eliminating the need for complete mask sets for each logic family variant. This allows selective transfer of only required layers, reducing mask-set costs and improving flexibility.
Solution Approach 2:
The patent transitions from planar 2D fabrication to 3D vertical stacking with layer transfer. Multiple logic family layers are stacked vertically, with each layer transferable independently. This dimensional change enables greater flexibility in configuring different logic families without requiring additional lateral space or complete mask sets for each configuration.
2Reliability
If traditional interconnect methods are used, then connections are established, but inter-chip interconnects dominate IC performance and power consumption
Solution Approach 1:
The patent moves interconnects from lateral 2D routing to vertical 3D pathways through TSVs and layer stacking. This reduces the physical distance signals must travel and eliminates the need for long inter-chip interconnects that dominate traditional designs. The vertical interconnect architecture inherently reduces both performance bottlenecks and power consumption.
Solution Approach 2:
The patent merges multiple logic family layers and their interconnects into a single integrated 3D structure. By combining what would traditionally be separate chips requiring external interconnects into one stacked device, the patent eliminates dominant inter-chip interconnects and reduces overall power consumption while improving performance.
3Productivity
If layer transfer techniques are employed, then TSV size and number are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary fabrication of logic family layers on separate donor substrates before transfer. This allows each layer to be optimized and prepared in advance, with TSVs and interconnects pre-formed. The preliminary action simplifies the final assembly process and reduces the complexity of managing complex 3D integration during manufacturing.
Solution Approach 2:
The patent introduces temporary donor substrates as intermediaries during the layer transfer process. These donor substrates simplify handling and processing of delicate logic layers during fabrication. The intermediaries are removed after transfer, having served their purpose of reducing manufacturing complexity during the critical transfer operations.
Data Source
AI summary
A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.