3D IC LDO Power Delivery Using a Stacked Cache Die
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Solution Overview
Problem
The semiconductor industry faces challenges in developing integrated circuits (ICs) with lower power consumption, better performance, smaller chip areas, and lower costs, as the complexity of processing and manufacturing increases with each generation, necessitating innovative approaches to improve power delivery and reduce silicon area costs.
Innovation Solution
The solution involves locating low-dropout (LDO) regulators in a cache die fabricated using a mature technology node, stacked underneath a compute die using advanced technology node, with power delivered vertically through hybrid bonding structures, reducing silicon area costs and improving power delivery performance by minimizing lateral distribution and IR drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If LDO regulators are located in the compute die, then power delivery is simplified, but silicon area cost increases
Solution Approach 1:
The patent moves LDO regulators from the traditional planar location in the compute die to a vertical stacking configuration in a separate cache die. This dimensional transition from 2D to 3D integration allows power delivery functionality to be separated from the compute die, reducing its area cost while maintaining simplified power delivery through vertical hybrid bonding interconnects.
Solution Approach 2:
The patent segments the compute die and cache die as separate functional units, with LDO regulators located in the cache die. This segmentation allows the compute die to focus on computation while the cache die handles power regulation, reducing the silicon area cost of the compute die and enabling specialized optimization of each component.
2Area of moving object
If LDO regulators are located in a separate cache die, then silicon area cost is reduced, but power delivery complexity increases
Solution Approach 1:
The patent utilizes vertical stacking and hybrid bonding to create direct vertical interconnects between the cache die (containing LDO regulators) and the compute die. This vertical dimensionality reduces lateral power distribution paths and minimizes IR drops, simplifying the overall power delivery architecture despite the physical separation of components.
3Device complexity
If traditional planar power distribution is used, then design is simpler, but IR drops increase
Solution Approach 1:
The patent transitions from planar (2D) power distribution to vertical (3D) power delivery through hybrid bonding interconnects. This vertical configuration significantly shortens the current path length between LDO regulators and compute die, reducing resistive losses and IR drops while maintaining design simplicity through standardized vertical stacking processes.
Data Source
AI summary
A three-dimensional integrated circuit (3D IC) package is provided. The 3D IC package includes: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction.