3D IC Logic Cell Stacking via Identical Layouts
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Solution Overview
Problem
Conventional 3D integrated circuits face challenges in scaling to a greater number of device tiers due to limitations in interconnection density, thermal budget, and increased mask numbers and process steps, making cost-effective fabrication of multi-layer 3D ICs difficult.
Innovation Solution
A 3D IC design featuring logic cells with identical network layouts and a single layer of horizontally extending conductive lines, allowing for parallel processing of multiple tiers with a reduced set of masks and process steps, enabling rational and cost-effective fabrication of up to 8, 16, or more device tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of device tiers is increased to improve system-level performance and area scaling, then productivity and energy efficiency are improved, but device complexity and fabrication cost increase due to more masks and process steps
Solution Approach 1:
The patent divides the 3D IC fabrication into modular logic cells, where each logic cell contains a complete set of transistors and interconnections. This segmentation allows identical logic cells to be replicated across multiple tiers using the same mask set, reducing fabrication complexity while enabling increased device tiers for improved performance
Solution Approach 2:
The patent uses identical logic cell designs across all device tiers, copying the same transistor layouts and interconnection patterns. This copying approach allows multiple tiers to be fabricated using the same mask set and process steps, reducing fabrication complexity while enabling scaling to greater numbers of tiers
2Quantity of substance
If conventional via interconnections are used to achieve greater via densities, then interconnection density is improved, but the number of masks and process steps increases, reducing ease of manufacture
Solution Approach 1:
The patent merges the via formation process with the standard logic cell fabrication process. Vias are formed as part of the logic cell structure using the same masks and process steps used for transistor and interconnection formation, eliminating the need for separate via processing and reducing overall fabrication complexity
Solution Approach 2:
The logic cell design serves multiple functions simultaneously: it provides the computational logic functionality, defines the via locations for interconnections, and establishes the interconnection pattern. This multi-functionality allows a single set of masks to accomplish what would traditionally require separate via masks and process steps
3Productivity
If TSVs are used for interconnection in parallel 3D integration, then stacking of several circuits is enabled, but the large footprint of TSVs limits interconnection density
Solution Approach 1:
The patent transitions from planar 2D interconnections to 3D vertical interconnections by forming vias that extend through the logic cell structure. This dimensional change allows interconnections to pass through the vertical dimension rather than requiring large lateral footprints, enabling higher interconnection density while maintaining circuit stacking capability
4Area of stationary object
If the number of device tiers is increased to achieve greater scaling, then area efficiency is improved, but thermal budget constraints from the bottom tier limit fabrication of subsequent tiers
Solution Approach 1:
The patent segments the fabrication process into identical, repeatable logic cell modules that can be fabricated independently and then stacked. This segmentation allows each tier to be processed with the same thermal budget constraints, making the fabrication process scalable to multiple tiers without compounding thermal challenges
Data Source
AI summary
According to an aspect of the present inventive concept there is provided 3D IC, comprising:a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors,wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, andwherein each logic cell comprises:a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, anda single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.