3D IC Logic Fabric with Re-programmable Antifuse and TSV
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the ability to produce a commercially viable range of products with different logic families, and existing 3D IC technologies are constrained by large Through-Silicon Vias (TSVs) that restrict the number of connections that can be made.
Innovation Solution
The development of a 3D IC device fabrication method using a re-programmable antifuse in conjunction with Through Silicon Via (TSV) to construct configurable logic, allowing for the creation of multiple connections less than one micron in size, enabling the use of 3D IC technology for various device applications, and incorporating a modular approach with Through-Silicon-Via (TSV) to construct configurable systems with repeating logic tiles and mixed-process dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent implements re-programmable antifuse technology that allows the logic fabric to be dynamically reconfigured after fabrication. This enables the same physical device to be programmed into different logic families (CMOS, BiCMOS, etc.) without requiring different mask sets, thereby achieving high adaptability while maintaining manufacturing simplicity.
Solution Approach 2:
The invention changes the operational parameters of the semiconductor device by using antifuse structures that can be programmed to different states. By varying the programming parameters of the antifuses rather than changing the physical fabrication parameters, the system achieves diverse logic family production without incurring additional mask-set costs.
2Productivity
If existing 3D IC technologies are used, then inter-chip connections are established, but Through-Silicon Vias are large which restricts the number of connections
Solution Approach 1:
The patent transitions from two-dimensional planar connections to three-dimensional vertical connections using Through-Silicon Vias. By utilizing the vertical dimension, the system achieves high-density inter-chip interconnects that pass through the substrate, enabling numerous connections without increasing the lateral footprint of individual vias.
Solution Approach 2:
The invention segments the interconnect structure into multiple layers of Through-Silicon Vias distributed across the substrate. This segmentation allows numerous small connections to be made in parallel, achieving high connection density without requiring each individual via to be large.
3Adaptability or versatility
If re-programmable antifuse with TSV is used, then flexibility and connection density are improved, but device complexity increases
Solution Approach 1:
The patent creates a universal logic fabric using re-programmable antifuses that can be configured to perform multiple logic functions. The same physical structure serves as both the interconnect and the logic element, eliminating the need for separate dedicated logic circuits and reducing overall device complexity despite the added configurability.
Solution Approach 2:
The invention merges the interconnect function and logic function into a single integrated structure. The Through-Silicon Vias serve both as physical connectors and as programmable logic elements when combined with the antifuse structures, thereby achieving high adaptability without proportionally increasing device complexity.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a plurality of second transistors atop at least a portion of the first metal layer, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where the plurality of second transistors are vertically oriented transistors, and where the plurality of second transistors are at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the plurality of second transistors, where the second metal layer is aligned to the first metal layer with less than 150 nm misalignment, and where at least one of the second transistors is a junction-less transistor.