Built-in Self-Test for 3D-IC Memory Repair
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Solution Overview
Problem
The existing system-on-chip architectures lack an efficient built-in self-test and repair capability for stacked memory integrated circuit dies, which are prone to defects due to increased complexity and density, requiring post-assembly testing that duplicates manufacturer-level testing and repair processes, and must accommodate various memory types and sources.
Innovation Solution
A memory controller with a built-in self-test system that includes a control processor and state machines for sequential testing and repair, using redundant memory portions, interfaced through a physical interface to detect and replace defective memory areas, accommodating different memory types and manufacturers' test and repair procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If post-assembly testing is performed on stacked memory integrated circuit dies, then defects can be detected, but the testing process duplicates manufacturer-level testing and reduces production efficiency
Solution Approach 1:
The patent combines manufacturer-level testing and post-assembly testing into a single unified testing process. The built-in self-test circuitry is integrated directly into the memory controller on the system-on-chip, allowing the same test functions to serve both quality assurance during manufacturing and defect detection after assembly, thereby eliminating duplication and improving production efficiency.
Solution Approach 2:
The patent implements testing capability in advance by incorporating built-in self-test circuitry into the memory controller before the memory system is assembled and deployed. This preliminary integration of test functions allows the system to perform comprehensive testing at the earliest possible stage, preventing the need for separate post-assembly testing and maintaining high production efficiency.
2Productivity
If built-in self-test circuitry is incorporated in the system-on-chip to identify assembly defects, then post-assembly testing efficiency is improved, but the device complexity increases
Solution Approach 1:
The patent implements multi-functionality by designing the built-in self-test circuitry to perform multiple testing functions across different memory types and organizations. The test controller can execute various test patterns, handle different memory architectures (such as 3D stacked memory), and accommodate different defect types, thereby achieving comprehensive testing capability without proportionally increasing circuit complexity.
Solution Approach 2:
The memory controller performs self-testing through built-in circuitry that automatically detects defects without requiring external testing equipment. The self-test module generates test patterns, applies them to the memory, and analyzes results autonomously, reducing the complexity burden by eliminating the need for complex external test equipment and manual testing procedures.
3Reliability
If repair capability is added to substitute redundant memory portions for defective portions, then system reliability is enhanced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent prepares for potential defects in advance by incorporating redundant memory portions into the memory architecture during the design and manufacturing stages. These spare memory elements are pre-positioned and configured but remain inactive during normal operation, ready to be activated only when defects are detected through the built-in self-test, thereby simplifying the manufacturing process while ensuring future reliability.
Solution Approach 2:
The patent introduces a repair controller as an intermediary component that manages the complex repair process. This dedicated controller handles defect detection, analyzes test results, determines appropriate repair actions, and coordinates the substitution of redundant memory portions, thereby isolating the complexity of repair operations from the main memory controller and simplifying overall manufacturing.
4Adaptability or versatility
If the built-in self-test function is designed to accommodate various memory types and memory integrated circuit dies from multiple sources, then adaptability is improved, but the testing and repair procedures become more complex
Solution Approach 1:
The patent implements a universal test controller that can adapt to different memory types, organizations, and manufacturers through a standardized interface. The controller includes configurable parameters and programmable test patterns that can be adjusted to match specific memory architectures, allowing a single unified testing and repair system to handle diverse memory components without requiring multiple specialized test systems.
Solution Approach 2:
The patent introduces dynamic adaptability through programmable and configurable test parameters that can be adjusted based on the specific memory type being tested. The test controller can dynamically modify test patterns, timing parameters, and repair procedures to match the characteristics of different memory integrated circuit dies, thereby managing complexity through flexibility rather than through multiple fixed systems.
Data Source
AI summary
A system-on-chip (SOC) (10) is interfaced with a memory (20) formed by a plurality of stacked memory integrated circuit dies (20a-20n). The SOC (10) includes a memory controller (100) that has a built-in self-test (BIST) system (1000) for performing the testing and repair of memory (20). BIST system (1000) includes a microcode processor (1130) that communicates externally to the SOC (10) through a Joint Test Action Group interface (120) and is coupled to a BIST state machine (1140) for executing a memory specific test sequence to detect faults in memory (20). The microcode processor (1130) further communicates with a repair state machine (1150) to execute memory specific repair procedures responsive to memory faults being detected.