3D Integrated Circuit Placement Using Multi-Strata Partitioning
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Solution Overview
Problem
Current CAD tools face challenges in optimizing the design of monolithic three-dimensional integrated circuits, particularly in minimizing the number of Through-Silicon Vias (TSVs) and leveraging dense inter-layer connectivity to enhance object placement and proximity in 3D space, which is not effectively addressed by traditional 2D design methodologies.
Innovation Solution
The development of CAD tool methodologies that perform partitioning and placement across multiple strata using 2D placers and routers, optimizing for disparate characteristics of each layer and leveraging dense inter-layer connectivity to improve physical design efficiency in monolithic 3D ICs, allowing for the use of existing 2D design tools in a 3D context.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional 2D design methodologies are used for 3D ICs, then existing 2D tools can be utilized, but the number of TSVs is not minimized and inter-layer connectivity is not optimized
Solution Approach 1:
The patent extends traditional 2D place-and-route methodologies into the third dimension by introducing multi-strata partitioning and placement algorithms. The system divides the 3D IC design space into multiple strata (layers) and performs placement operations across these strata, enabling optimization of TSV placement and inter-layer connectivity while maintaining compatibility with existing 2D tool frameworks.
2Adaptability or versatility
If TSVs are used for inter-layer connections, then 3D stacking is enabled, but the number of TSVs increases and manufacturing complexity increases
Solution Approach 1:
The patent segments the 3D IC design into multiple strata or layers, allowing independent optimization of each layer's placement and routing. This segmentation enables the system to minimize TSV requirements by confining connections within strata where possible and reducing the need for vertical inter-layer connections, thereby decreasing the overall number of TSVs while maintaining 3D stacking capability.
3Productivity
If dense inter-layer connectivity is leveraged, then placement efficiency improves, but the complexity of optimizing object placement across multiple layers increases
Solution Approach 1:
The patent introduces a multi-strata framework that adds a vertical dimension to traditional 2D placement algorithms. By organizing objects into multiple strata and defining placement rules that operate across these strata, the system enables dense inter-layer connectivity while managing optimization complexity through structured layer-specific constraints and objectives.
Data Source
AI summary
A method of designing a 3D Integrated Circuit, the method including: partitioning at least one design into at least two levels, a first level and a second level; providing placement data of the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; and performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.