Two-Chip Co-Design for 3D IC Net Assignment Optimization
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Solution Overview
Problem
Current 3D IC design technologies face challenges in optimizing inter-chip connections between stacked chips using through-silicon-vias (TSVs) and micro-bumps (MBs, as existing methods often result in suboptimal wire length and routing due to limited user discretion and differential weighting of signal and RDL routing layers.
Innovation Solution
A method involving a two-chip co-design technique that uses a bipartite matching algorithm, specifically an expanded Munkres algorithm, to determine optimized inter-chip path and IO pair combinations by calculating costs based on planar distances and layer weights, allowing for simultaneous processing of two chips to achieve global optimum solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If single-chip net assignment is used to assign TSVs to MBs, then the design process is simpler, but the total wire length is suboptimal and routing efficiency is reduced
Solution Approach 1:
The patent combines two separate single-chip net assignment processes into a unified two-chip co-design net assignment process. The system simultaneously considers TSV assignments on both chip1 and chip2, along with inter-chip signal assignments, to minimize total wire length across the entire 3D IC stack rather than optimizing each chip independently.
Solution Approach 2:
The patent extends the traditional single-chip 2D net assignment problem into a three-dimensional optimization space by incorporating inter-chip connections and TSV assignments from both chips. The objective function minimizes weighted wire length across multiple dimensions including intra-chip routing on chip1, intra-chip routing on chip2, and inter-chip TSV assignments.
2Manufacturing precision
If inter-chip signals are assigned after intra-chip paths are determined, then the design flow is sequential and simpler, but the total weighted wire length cannot be globally optimized
Solution Approach 1:
The patent performs preliminary actions by simultaneously establishing all TSV assignments on both chips and all inter-chip signal assignments in a single coordinated optimization process. Rather than sequentially determining intra-chip paths first and then inter-chip assignments, the system pre-coordinates all assignments together to achieve global optimality.
Solution Approach 2:
The patent replaces the sequential mechanical design flow with an integrated computational optimization system. The unified objective function and constraint system computationally coordinate TSV assignments and inter-chip signal assignments simultaneously, substituting iterative sequential design steps with a single global optimization calculation.
3Adaptability or versatility
If TSVs and MBs are placed with fixed spacing in arrays, then manufacturing is easier, but user discretion for optimization is limited
Solution Approach 1:
The patent applies local quality by allowing different weighting factors for different types of wire segments in the objective function. Specifically, wires on signal routing layers are weighted differently from wires on RDL routing layers, enabling localized optimization priorities in different regions of the design while maintaining the overall array structure of TSVs and MBs.
Data Source
AI summary
A method of generating optimized input/output (IO) pair and inter-chip connection combinations for two chips is described. In this method, first and second designs for two chips can be specified. Then inter-chip signals based on the first and second designs can be specified. IO pairs for the first and second chips can be determined based on the inter-chip signals. At this point, electrical contacts between micro-bumps (MBs) of the first and second chips can be formed. Inter-chip paths with through-silicon-vias (TSVs) and MBs of the first and second chips can also be formed. At this point, the costs of assigning the IO pairs to the inter-chip paths can be determined. A cost matrix can be built based on these costs. A bipartite matching algorithm can be applied to the cost matrix to determine the optimized IO pair and inter-chip path combinations.