3D IC Backside Connections Using Offset Bumps and Thick Metal Lines
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Solution Overview
Problem
The existing backside connections in 3D wafer stacks face limitations in delivering sufficient electrical power and suffer from mechanical stress, leading to reliability issues and complex, costly manufacturing processes.
Innovation Solution
The implementation of offset conductive bumps and thick conductive lines that connect to backside vias, improving power delivery and reducing mechanical stress through a simplified manufacturing flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conductive bumps are placed directly on top of vias to form backside connections, then the manufacturing process is simplified, but the electrical power delivery capability is limited and mechanical stress increases
Solution Approach 1:
The patent transitions from direct vertical alignment (1D) to offset lateral positioning (2D), creating a thick conductive line that extends laterally from the via to the bump. This dimensional change allows the conductive path to distribute stress and increase power delivery cross-section without compromising manufacturing simplicity.
Solution Approach 2:
The backside connection structure combines multiple materials: copper vias, thick copper conductive lines, and solder bumps. This composite approach creates a robust power delivery path that leverages the high conductivity of copper and the reliable bonding of solder, resolving the power delivery limitation.
2Ease of manufacture
If conductive bumps are placed directly on top of vias, then alignment is simplified, but direct vertical stress transfer deteriorates thermal and mechanical stability
Solution Approach 1:
The thick conductive line acts as an intermediary element between the via and the bump, decoupling their direct vertical connection. This mediator distributes mechanical and thermal stress laterally along its extended path, preventing stress concentration at the via-bump interface while maintaining electrical connectivity.
Solution Approach 2:
By extending the conductive path laterally in the horizontal dimension rather than maintaining direct vertical alignment, the structure dissipates stress across a larger area and reduces the vertical stress transfer path, thereby improving thermal and mechanical stability.
3Reliability
If additional operations are added to provide re-routing capabilities and increase power delivery, then power delivery and functionality are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The thick conductive line serves multiple functions simultaneously: it provides re-routing capability, increases power delivery cross-section, and acts as a stress buffer. This multi-functionality eliminates the need for separate dedicated structures for each function, simplifying the overall manufacturing process while achieving all desired improvements.
Solution Approach 2:
The patent merges the re-routing function and power delivery function into a single thick conductive line structure. By combining these functions that would traditionally require separate operations and structures, the manufacturing process remains simple while achieving enhanced power delivery and routing flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances electrical power delivery and mechanical stability, reducing stress on the low-k ILD layer and chip-package interface, while simplifying the manufacturing process for 3D wafer stacks.
Implementation Method 1
thick conductive lines that connect to backside vias, improving power delivery
Implementation Method 2
The direct vertical stress transfer into dielectric layer 108 and to an interface between 3D wafer stack 100 and a package (not shown) is reduced by offsetting conductive bumps from backside vias
Data Source
AI summary
Backside connections for 3D integrated circuits and methods to fabricate thereof are described. A stack of a first wafer over a second wafer that has a substrate of the first wafer on top of the stack, is formed. The substrate of the first wafer is thinned. A first dielectric layer is deposited on the thinned substrate. First vias extending through the substrate to the first wafer are formed in the first dielectric layer. A conductive layer is deposited in the first vias and on the first dielectric layer to form thick conductive lines. Second dielectric layer is formed on the conductive layer. Second vias extending to the conductive lines are formed in the second dielectric layer. Conductive bumps extending into the second vias and offsetting the first vias are formed on the second dielectric layer.