3D IC Via Structure With ONO Layer for Stable TSV Deposition
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Solution Overview
Problem
Existing 3D IC technologies face challenges with deposition uniformity variations and increased resistance and power consumption due to the need for narrower and taller through silicon vias (TSVs) in advanced packages, which degrade performance.
Innovation Solution
A semiconductor structure featuring a bottom wafer with a bottom substrate and interconnect structure, a top wafer with a top substrate and interconnect structure directly bonded via copper pads, an oxide-nitride-oxide (ONO) dielectric layer, and conductive vias extending into the ONO layer and substrate, with aligned vertical sidewalls covered by a protective layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If TSVs are made narrower and taller to integrate more interconnects and accommodate taller stacks of chips, then the number of interconnects and stacking capability are improved, but deposition uniformity deteriorates and resistance and power consumption increase
Solution Approach 1:
The patent segments the continuous TSV structure into discrete components: separate liner layers (first liner layer, second liner layer), distinct dielectric layers, and segmented conductive material deposition. This segmentation allows independent optimization of each component's deposition process, improving overall uniformity even in narrow and tall TSV structures
Solution Approach 2:
The patent applies preliminary actions by forming the liner layer and dielectric layer structures before filling with conductive material. The liner layer is pre-formed to define the TSV boundaries, and dielectric layers are pre-deposited to provide structural support and insulation, enabling controlled and uniform subsequent conductive material deposition
2Productivity
If TSVs are made narrower and taller to integrate more interconnects, then integration density is improved, but resistance increases
Solution Approach 1:
The patent changes material parameters by using copper as the conductive material instead of traditional aluminum, which has lower resistivity. The liner layer material and thickness parameters are also optimized to ensure uniform deposition and reduce interface resistance, thereby reducing overall TSV resistance despite narrower dimensions
Solution Approach 2:
The patent employs composite material structures consisting of multiple layers: liner layers (e.g., tungsten, tantalum), dielectric layers, and copper fill material. This composite structure optimizes each layer's properties for its specific function, resulting in TSVs with reduced resistance while maintaining narrow dimensions for high integration density
3Productivity
If TSVs are made narrower and taller to accommodate taller stacks of chips, then stacking capability is improved, but power consumption increases
Solution Approach 1:
The patent changes the conductive material parameter to copper, which has approximately 6 times lower resistivity than aluminum. This parameter change reduces the resistance in narrow and tall TSV structures, thereby reducing power consumption (P=I²R) while maintaining the stacking capability enabled by the taller TSV geometry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances performance and reduces resistance and power consumption by stabilizing via deposition and improving signal integrity in 3D integrated circuits.
Implementation Method 1
Chip-to-wafer and wafer-to-wafer hybrid bonding can be used to connect chips using direct, copper-to-copper bonds that enable the combined elements to perform as one
Implementation Method 2
An oxide-nitride-oxide (ONO) dielectric layer covering the rear surface of the top substrate
Implementation Method 3
They are formed by etching trenches into silicon and then filling them with insulating liners and metal wires
Data Source
AI summary
A semiconductor structure includes a bottom wafer having a bottom substrate and a bottom interconnect structure on the bottom substrate, and a top wafer having a top substrate with a front surface and a rear surface and a top interconnect structure disposed on the front surface of the top substrate. The top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer. An oxide-nitride-oxide (ONO) dielectric layer covers the rear surface of the top substrate. A plurality of conductive vias is disposed on the rear surface and extending into the ONO dielectric layer and the top substrate.