3D IC Pick-and-Place Assembly for Overlay Precision and Security
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Solution Overview
Problem
Conventional semiconductor manufacturing faces challenges in scaling beyond 20 nm features due to physical, material, power-thermal, and technological limitations, leading to increased production costs without commensurate performance gains, and there are issues with hardware security and intellectual property violations in the supply chain.
Innovation Solution
Employing nano-precise pick-and-place assembly techniques with prefabricated blocks (PFBs) and mixed-integer programming (MIP) for 3D IC and M2A2 design, utilizing moiré-based metrology and nano-imprint lithography steppers for precise overlay correction, and a split-fabrication approach to ensure hardware security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used for patterning sub-20 nm features, then manufacturing capability is maintained, but manufacturing precision deteriorates due to physical and material limitations
Solution Approach 1:
The patent segments the monolithic fabrication process into multiple discrete steps using self-aligned double patterning (SADP). The first mandrel pattern is formed, then spacer material is deposited and etched to create the final sub-20 nm features. This segmentation enables precise patterning at scales where conventional single-step lithography fails.
Solution Approach 2:
Mandrels are formed as preliminary structures that define the initial pattern before the actual sub-20 nm features are created. These mandrels serve as templates for subsequent spacer deposition, enabling precise feature placement without requiring direct patterning at the final scale.
2Productivity
If transistor scaling continues to improve performance, then computing capability increases, but production cost increases due to complex multiple-patterning requirements
Solution Approach 1:
The fabrication process is segmented into modular stages (mandrel formation, spacer deposition, etching) that can be independently optimized and reused. This modularity reduces overall process complexity compared to conventional multiple-patterning approaches, lowering production costs while enabling advanced node manufacturing.
Solution Approach 2:
Spacer material acts as an intermediary that translates the larger-scale mandrel pattern into the final sub-20 nm features. This intermediary approach enables precise feature creation without requiring direct patterning at the极限 scale, simplifying the manufacturing process.
3Area of stationary object
If transistor size is reduced to increase density, then area utilization improves, but reliability deteriorates due to increased tunneling and leakage currents
Solution Approach 1:
The patent employs selective spacer deposition and targeted etching processes that create locally optimized feature geometries. By controlling the spacer thickness and composition in specific regions, the design maintains reliable electrical characteristics even at reduced transistor dimensions, addressing tunneling and leakage issues through localized structural control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables ultra-high density heterogeneous integration, reduces production costs, and ensures hardware security by allowing fabrication at trusted facilities, while maintaining lithographic precision and addressing scaling limitations.
Implementation Method 1
a moiré-based metrology mechanism configured to sense overlay errors when assembling the one or more dies in the first substrate onto the second substrate
Implementation Method 2
nanoprinting steppers for precise overlay correction
Data Source
AI summary
Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.