3D Single-Crystal IC Stacking With Direct Oxide Bonding
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and existing 3D IC technologies are constrained by large Through-Silicon-Vias (TSVs) that restrict the number of connections that can be made.
Innovation Solution
The development of a 3D IC device fabrication method using a programmable antifuse structure with Through-Silicon-Via (TSV) technology, enabling the construction of configurable logic devices with reduced TSV size and increased connectivity, allowing for the creation of multiple layers with direct oxide-to-oxide bonds and localized back bias circuits for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Through-Silicon-Via (TSV) technology is used to create 3D IC connections, then connectivity between layers is enabled, but the large size of TSVs restricts the number of connections that can be made
Solution Approach 1:
The patent segments the connection structure into multiple components: smaller TSVs for vertical connections, direct oxide-to-oxide bonds for lateral connections, and raised source/drain transistor structures for localized functionality. This segmentation allows numerous connections to be made without requiring large individual TSVs, thereby increasing connectivity density while reducing the size constraint of each individual via.
Solution Approach 2:
The patent introduces direct oxide-to-oxide bonds as an additional connection dimension alongside vertical TSVs. This creates a two-dimensional connection network (vertical TSVs plus lateral oxide bonds) that significantly increases the number of possible connections without increasing TSV size, resolving the contradiction between connectivity density and via size.
2Adaptability or versatility
If conventional fabrication methods are used, then manufacturing processes are established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent employs universal oxide-to-oxide bonding that can be applied across different logic families and product types without requiring family-specific mask sets. The raised source/drain structures and direct bonding methodology provide a universal fabrication approach that reduces mask-set costs while maintaining flexibility to produce diverse logic, memory, and analog functions.
Solution Approach 2:
The patent changes the fabrication parameter from conventional metal-to-metal bonding to direct oxide-to-oxide bonding. This parameter change eliminates the need for complex mask sets and enables a simpler, more flexible manufacturing process that can be adapted to different product requirements without incurring high mask-set costs.
3Strength
If direct oxide-to-oxide bonds are used for layer bonding, then bonding strength is improved, but precise alignment is required
Solution Approach 1:
The patent performs preliminary alignment marker formation and oxide layer preparation before the actual bonding process. Alignment markers are pre-formed on the oxide layers, and the layers are pre-positioned and held in place during bonding. This preliminary action ensures precise alignment is achieved before bonding occurs, enabling strong oxide-to-oxide bonds without compromising alignment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, enhances flexibility in producing various logic, memory, and analog functions, and enables a higher density of connections in 3D ICs, overcoming the limitations of traditional TSV technology.
Implementation Method 1
the bonded includes direct oxide-to-oxide bonds
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a raised source or raised drain transistor structure, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.