3D IC Oxide-to-Oxide Bonding for Vertical Connectivity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing cost of mask sets for semiconductor manufacturing, particularly for custom products targeting smaller volume and less diverse markets, and the limitations of current 3D IC technologies due to large Through-Silicon-Via (TSV) size, which restricts vertical connectivity and leads to high development costs and performance issues.
Innovation Solution
The development of multilayer or Three Dimensional Integrated Circuit (3D IC) devices using single crystal transistors with oxide-to-oxide bonds and hybrid bonds, enabling layer transfer techniques to reduce lithography steps and improve vertical connectivity, and the use of alternative architectures to enhance yield and reliability, such as SmartCut and ELTRAN processes for constructing 3D ICs with reduced development costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through-Silicon-Via (TSV) technology is used to construct 3D stacked integrated circuits, then multiple layers of transistors can be bonded and connected vertically, but the large TSV size restricts vertical connectivity and increases development costs
Solution Approach 1:
The patent segments the TSV structure into multiple smaller vias arranged in arrays, replacing single large TSVs with grids of smaller TSVs. This segmentation enables higher density vertical connectivity while reducing the size constraint of individual vias, allowing more efficient interlayer communication in 3D ICs
Solution Approach 2:
The patent transitions from two-dimensional planar interconnects to three-dimensional vertical interconnects through TSVs, enabling stacking of multiple transistor layers. This dimensional change allows vertical connectivity between layers while the segmented TSV approach optimizes the utilization of this third dimension
2Productivity
If mask set cost increases for new process technology, then device density and functionality improve through scaling, but development costs become prohibitive for custom products targeting smaller volume markets
Solution Approach 1:
The patent develops universal 3D IC fabrication processes and standardized TSV structures that can be applied across multiple product types and process nodes. This universality allows the same base process to serve both high-volume standard products and low-volume custom products, amortizing the mask set cost across diverse applications
Solution Approach 2:
The patent performs preliminary process development and standardization of 3D IC fabrication techniques before they are widely adopted. By establishing reusable process modules, bonding methodologies, and design frameworks in advance, the patent enables smaller volume custom products to leverage pre-developed IP and processes, reducing their development costs
3Productivity
If wires (interconnects) are scaled down to improve transistor density, then transistor performance improves, but wire performance degrades and wires dominate power consumption
Solution Approach 1:
The patent moves interconnect routing from two-dimensional planar wires to three-dimensional vertical TSVs and through-silicon pathways. This dimensional transition shortens the effective interconnect length by routing vertically through the substrate, reducing resistance and capacitance, thereby lowering power consumption while maintaining high transistor density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides an order of magnitude improvement in vertical connectivity, reduces development costs, and enhances the yield and reliability of complex 3D ICs, making them suitable for future generations of ICs by allowing more efficient integration of transistors and memory cells with reduced interconnect lengths.
Implementation Method 1
first bond regions comprising first oxide to oxide bonds, wherein said first bond regions are disposed between said first level and said second level
Implementation Method 2
bond regions comprising hybrid bonds, said bond regions are disposed between said first level and said second level
Data Source
AI summary
A 3D device including: a first level including first single crystal transistors overlaid by a second level including second single crystal transistors; a third level including third single crystal transistors, the second level is overlaid by the third level; a fourth level including fourth single crystal transistors, the third level is overlaid by the fourth level; first bond regions including first oxide to oxide bonds, where the first bond regions are between the first level and the second level; second bond regions including second oxide to oxide bonds, where the second bond regions are between the second level and the third level; and third bond regions including third oxide to oxide bonds, where the third bond regions are between the third level and the fourth level, where the second level, third level, and fourth level each include one array of memory cells, and where the one array of memory cells is a DRAM type memory.