3D IC Buried Oxide Grounding Structure for Breakdown Voltage
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Solution Overview
Problem
Existing 3D integrated circuits (ICs) face challenges in improving electrical performance, particularly due to charge accumulation in buried oxide layers during manufacturing, which can affect the breakdown voltage of transistors.
Innovation Solution
A semiconductor device is fabricated using a first wafer with a first interconnection layer and a second wafer with a buried oxide layer and a semiconductor layer. The wafers are bonded, and a dielectric layer is formed on the buried oxide layer. A first metal structure is created to physically contact the buried oxide layer, grounding it and forming a charge release path to prevent charge accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wafer-level bonding and TSV technologies are used to form 3D IC, then space utilization is improved and signal transmission distance is reduced, but charge accumulation occurs in buried oxide layers affecting transistor breakdown voltage
Solution Approach 1:
The patent extracts the problematic charge accumulation issue by introducing a dedicated charge release path through the buried oxide layer. A metal structure (via) is formed to extend through the buried oxide layer and connect to a contact structure, providing a pathway for charges to be released from the buried oxide layer to the interconnection layer, thereby preventing charge accumulation and maintaining transistor breakdown voltage.
Solution Approach 2:
The patent introduces an intermediary charge release path consisting of a metal structure and contact structure that mediates between the buried oxide layer and the interconnection layer. This intermediary structure facilitates charge dissipation without disrupting the primary bonding and interconnection functions of the 3D IC, effectively resolving the charge accumulation problem while maintaining the benefits of wafer-level bonding and TSV technologies.
2Ease of manufacture
If conventional bonding methods are used, then manufacturing process is simple, but electrical performance of 3D IC cannot be improved
Solution Approach 1:
The patent applies preliminary action by forming the charge release path (metal structure through buried oxide layer connecting to contact structure) before or during the bonding process. This preliminary structure is prepared in advance to prevent charge accumulation issues that would otherwise degrade electrical performance, allowing the bonding process to proceed with improved electrical characteristics without requiring complete process redesign.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device effectively improves electrical performance by preventing charge accumulation in the buried oxide layer, thereby maintaining the breakdown voltage of transistors and enhancing overall device performance.
Implementation Method 1
A three-dimensional integrated circuit (3D IC) refers to a three-dimensional stack of chips formed by using wafer-level bonding and through silicon via (TSV) technologies
Implementation Method 2
The first metal structure is disposed through the dielectric layer, in which an end of the first metal structure physically contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure
Data Source
AI summary
A semiconductor device includes a first wafer, a second wafer, a dielectric layer and a first metal structure. The first wafer includes a first substrate and a first interconnection layer disposed on the first substrate. The second wafer includes a second substrate and a second interconnection layer. The second substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer. The second interconnection layer is disposed on the semiconductor layer, in which the second interconnection layer is bonded with the first interconnection layer. The dielectric layer is disposed on the buried oxide layer. The first metal structure is disposed through the dielectric layer, in which an end of the first metal structure physically contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.