3D IC Semiconductor Package Without Silicon Bridges
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Solution Overview
Problem
The use of silicon bridges in semiconductor packages can lead to movement or incorrect attachment during manufacturing, resulting in decreased yield and warpage due to thermal expansion differences between silicon and organic substrates.
Innovation Solution
A semiconductor package design that eliminates silicon bridges by using three-dimensional integrated circuit structures with interposers and redistribution layers to connect high-performance semiconductor chips to a substrate, enabling fine pitch I/O connections without silicon bridges, and employing molding materials and insulation members for structural support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If silicon bridges are used to connect semiconductor chips to substrates, then fine pitch I/O connections can be achieved, but the silicon bridges may move or be incorrectly attached during manufacturing, decreasing yield
Solution Approach 1:
The patent removes the silicon bridge component entirely from the system, replacing it with a direct bonding approach between the semiconductor chip and substrate. This extraction of the problematic intermediate component eliminates the movement and misalignment issues that occurred during manufacturing, thereby improving both attachment precision and manufacturing yield.
Solution Approach 2:
The patent employs asymmetric material selection by using an organic substrate with higher thermal expansion coefficient paired with a silicon-based semiconductor chip. This asymmetric combination, when directly bonded without silicon bridges, creates a more stable structural relationship that prevents manufacturing defects while maintaining fine pitch I/O connectivity.
2Manufacturing precision
If silicon bridges are embedded in the semiconductor substrate, then fine pitch I/O connections are enabled, but warpage occurs due to thermal expansion differences between silicon and organic materials
Solution Approach 1:
The patent extracts the silicon bridge component that caused thermal expansion mismatch and subsequent warpage. By directly bonding the semiconductor chip to the organic substrate without the intermediate silicon bridge, the patent eliminates the source of differential thermal expansion, thereby maintaining connection precision while improving package flatness and stability.
Solution Approach 2:
The patent changes the material parameter combination by directly bonding silicon-based chips to organic substrates without intermediate silicon layers. This parameter change in the material stack eliminates the thermal expansion differential that caused warpage, while advanced bonding techniques maintain the required connection precision for fine pitch I/O.
3Productivity
If more silicon bridges are used to increase integration density, then more connections are achieved, but the risk of movement and incorrect attachment increases
Solution Approach 1:
The patent removes the silicon bridge component entirely, replacing the approach of adding more silicon bridges with direct chip-to-substrate bonding. This extraction eliminates the fundamental reliability issues associated with silicon bridge attachment, allowing for increased integration density without proportionally increasing the risk of manufacturing defects.
Solution Approach 2:
The patent merges the functions of multiple silicon bridges into a single direct bonding interface between the semiconductor chip and substrate. By combining these connection functions, the patent achieves high integration density while reducing the total number of attachment points, thereby improving manufacturing yield through fewer potential failure points.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances yield by preventing silicon bridge-related issues and simplifies the package structure, while ensuring reliable signal routing and thermal management through the use of interposers and redistribution layers.
Implementation Method 1
the interposer electrically connects a fine pitch I/O of high-performance semiconductor chips within the upper semiconductor die and a normal pitch I/O of a semiconductor substrate
Implementation Method 2
the semiconductor substrate may include electrical routing that relays signals between the upper semiconductor dies of the three-dimensional integrated circuit (3D IC) structures
Data Source
AI summary
A semiconductor package includes a substrate, a first three-dimensional integrated circuit structure on the substrate, and a second three-dimensional integrated circuit structure on the substrate, where the first three-dimensional integrated circuit structure may include a first interposer including a first semiconductor die, and a second semiconductor die on the first interposer, where the second three-dimensional integrated circuit structure may include a second interposer including a third semiconductor die, and a fourth semiconductor die on the second interposer, where the substrate may include an electrical routing configured to relay a signal from the second semiconductor die and a signal from the fourth semiconductor die.