3D IC Package Coplanarity via Embedded Substrate Cavities
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Solution Overview
Problem
Three-dimensional integrated circuit (IC) systems in packages face manufacturing challenges due to complex processes, increased cost, and reliability issues caused by varying component heights and thicknesses, which complicate the formation of even surfaces in stacked packages.
Innovation Solution
The method involves embedding components of different thicknesses in cavities of a prefabricated substrate using high viscosity epoxy to create a uniform surface, with an automated component placement system ensuring coplanarity, and additional epoxy to fill gaps, allowing for standard interconnect layer formation without the need for chemical-mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If components of different thicknesses are stacked in a three-dimensional package, then component integration is achieved, but surface uniformity deteriorates
Solution Approach 1:
The patent applies local quality by providing each component with an individual cavity that is customized to match the specific thickness of that component. This allows each component to be embedded at the correct depth to achieve a uniform top surface, while accommodating variations in component thickness. The cavity depth is locally adjusted for each component rather than using a uniform approach.
Solution Approach 2:
The patent employs preliminary action by pre-forming cavities in the substrate before component placement. These cavities are designed with specific depths corresponding to each component's thickness, so that when components are placed in the cavities, their top surfaces automatically align to form a uniform plane without requiring subsequent planarization processes.
2Manufacturing precision
If complex planarization processes are used to achieve even surfaces, then surface uniformity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent eliminates complex planarization processes by performing the surface leveling action in advance during substrate fabrication. Cavities of appropriate depths are pre-formed in the substrate before component placement, so that components naturally sit at the correct heights when installed, achieving surface uniformity without requiring chemical-mechanical polishing or other complex planarization steps afterward.
Solution Approach 2:
The patent extracts the surface planarization function from the post-assembly process and transfers it to the substrate fabrication stage. Instead of applying planarization processes to the completed stack, the solution removes the need for such processes by incorporating the leveling function into the cavity formation step during substrate manufacturing.
3Adaptability or versatility
If traditional SiP manufacturing processes are used, then component stacking is achieved, but manufacturing time and cost increase
Solution Approach 1:
The patent improves manufacturing efficiency by performing preliminary cavity formation and component placement in an optimized sequence. Cavities are pre-formed in the substrate, allowing components to be placed directly into their final positions without requiring subsequent planarization or repositioning steps, thereby reducing overall manufacturing time and cycle time.
Solution Approach 2:
The patent applies segmentation by dividing the substrate into multiple regions with individually tailored cavities for different components. This allows parallel processing and assembly of multiple components with different thicknesses simultaneously, improving throughput and manufacturing efficiency compared to sequential approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and enhances reliability by ensuring even surfaces for interconnect layer formation, enabling efficient assembly of package-on-package and surface mount devices without the need for complex planarization processes.
Implementation Method 1
A relatively high viscosity epoxy can be used to make sure the die and component stay in the place after placement
Data Source
AI summary
A method for making a packaged semiconductor device includes dispensing a first adhesive into a first cavity of a substrate having a first major surface and a second major surface. The first cavity extends into the substrate from the second major surface. The method further includes placing a first component having a thickness less than a thickness of the substrate into the first cavity such that the first adhesive physically contacts a first major surface of the first component and at least partially fills a gap between sidewalls of the first component and sidewalls of the first cavity. After placing the first component, a second major surface of the first component is coplanar with the second major surface of the substrate.