3D IC Package Layout With Back-Side Memory Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating high-density three-dimensional integrated circuit packages due to limitations in bonding integrated circuit chips onto substrates, where two-dimensional integration density has surpassed the ability to redistribute ball contact areas effectively, necessitating innovative solutions for enhanced performance and memory capacity.
Innovation Solution
The formation of integrated circuit packages involves fabricating active devices and circuit elements on both sides of a substrate, with a front-side and back-side interconnect structure, including through-silicon vias and hybrid bonding techniques to balance memory arrays and power delivery networks, allowing for flexible weighting and improved performance by incorporating both legacy and advanced technology devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional integration density is increased by reducing minimum feature size, then more components can be integrated into a given area, but the ability to bond an integrated circuit chip onto a substrate becomes insufficient
Solution Approach 1:
The patent transitions from two-dimensional integration to three-dimensional integration by stacking multiple chips vertically. This dimensional change allows continued increase in integration density without further reducing feature sizes, thereby avoiding the bonding limitations that arise in 2D scaling. The 3D architecture enables more components to be integrated by utilizing the vertical dimension rather than being constrained to the substrate surface.
2Area of stationary object
If interposers are used to redistribute ball contact areas, then a larger area is available for bonding, but the device complexity increases
Solution Approach 1:
The patent integrates multiple functional elements directly onto the chip surface, including memory cells, logic circuits, and bonding pads, eliminating the need for separate interposer structures. This merging of functions reduces overall device complexity while maintaining adequate bonding area through direct chip-to-substrate or chip-to-chip bonding interfaces.
Solution Approach 2:
The patent divides the integrated circuit into multiple stacked chips, each performing specific functions. This segmentation allows each chip to have optimized bonding areas and reduces the complexity of any single chip while achieving high overall integration density through the stacked configuration.
3Quantity of substance
If three-dimensional packages with multiple chips are developed, then memory capacity and performance are enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent employs wafer-level processing where multiple chips are fabricated and prepared in parallel on wafers before being stacked and bonded. This preliminary action at the wafer level simplifies the subsequent packaging process by pre-assembling multiple chips with their interconnect structures already formed, reducing the complexity of manual chip-by-chip assembly and enabling higher throughput manufacturing.
Data Source
AI summary
In an embodiment, a method includes forming a device layer over a first substrate; forming a first interconnect structure over a front-side of the device layer; attaching a second substrate to the first interconnect structure; forming a second interconnect structure over a back-side of the device layer, the second interconnect structure comprising back-side memory elements, wherein the back-side memory elements and a first plurality of active devices of the device layer provide a first memory array; and forming conductive connectors over the second interconnect structure.